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acer laboratories inc. --preliminary, confidential, proprietary-- m512x : mega i/o controller with pnp 07-02-1997 document number: 512xds02.doc page 1 acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, r.o.c. tel: 886-(02) 762-8800 fax: 762-6060 m512x : mega i/o controller with plug & play supports windows 95 plug and play supports 2 serial/1 parallel/fdc/rtc/kb and ps/2 mouse functions supports 22 general purpose i/o pins enhanced esd/latch up to over 4kv/300 ma supports spp, ps/2, epp, ecp and 1284 compliance supports 5 gpio alternative function pins for remote control supports ir via uart1, uart2 and two additional ir pins supports fast gate a20 and rc functions supports kbc and rtc enable/disable functions single-chip notebook/desktop solution features n supports windows 95 plug-and-play n supports 2 serial / 1 parallel / fdc / rtc / kb / ps/2 mouse functions n supports 22 general purpose i/o pins - 3 gpio ports (ports 1, 2, 3) - 5 gpio-alt function pins for remote control (pins 30-34) - 2 gen eral purpose chip select pins (pins 24-25) - supports i 2 c control pins n 2.88 mb floppy disk controller - software compatible with 82077 and supports 16-byte data fifos - high performance internal data separator - supports standard 1 mbps / 500 kbps / 300 kbps / 250 kbps data rate - supports 3 modes of 3.5" fdd (720k/1.2m/1.44mb) - swappable drives a and b n supports fdc through parallel port pins n supports at ps/2 kb and ps/2 mouse n built-in keyboard controller and real time clock n various modes of parallel port supports ecp/ epp / ps/2 / spp and 1284 compliance - ibm pc/xt, pc/at and ps/2 compatible bi-directional parallel port - enhanced parallel port (epp) compatible - microsoft and hewlett packard extended capabilities port (ecp) compatible n serial ports - two high performance 16550 compatible uarts with send/receive 16-byte fifos - serial infra red (sir) for wireless communications - midi (musical instrument digital interface) compatible n high performance power management for fdc, uart and parallel port n supports xd-to-sd bus buffer and control pins n supports enable/disable kbc and rtc n supports fast gate a20 and rc function n supports external kbc programming pin functions n supports additional irda and ask ir pins n supports phoenix kbc (m5123), ami kbc(M5125) n 160-pin pqfp package
--preliminary, confidential, proprietary-- acer laboratories inc. m512x : mega i/o controller with pnp page 2 07-02-1997 document number: 512xds02.doc acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, roc tel: 886-(02) 762-8800 fax: 762-6060 table of contents : section 1 : introduction ................................ ................................ ................................ .............. 3 1.1 features and function ................................ ................................ ................................ 3 1.2 block diagram ................................ ................................ ................................ ............ 4 1.3 register overview ................................ ................................ ................................ ...... 5 section 2 : pin description ................................ ................................ ................................ ......... 6 2.1 pinout diagram ................................ ................................ ................................ .......... 6 2.2 pin de scription ................................ ................................ ................................ ........... 7 2.3 numerical pin list ................................ ................................ ................................ ...... 13 2.4 alphabetical pin list ................................ ................................ ................................ ... 15 section 3 : configuration description and power management features ................................ 17 3.1 configuration port ................................ ................................ ................................ ...... 17 3.2 power management features ................................ ................................ ..................... 29 section 4 : floppy disk controller ................................ ................................ .............................. 31 4.1 register overview ................................ ................................ ................................ ...... 31 4.2 register description ................................ ................................ ................................ ... 32 4.3 result phase status registers ................................ ................................ .................... 39 4.4 processor software interface ................................ ................................ ...................... 41 4.5 command set descriptions ................................ ................................ ........................ 42 4.6 command description table ................................ ................................ ...................... 51 section 5 : serial port registers ................................ ................................ ................................ 58 5.1 line control register ................................ ................................ ................................ .. 60 5.2 programmable ba ud generator ................................ ................................ .................. 61 5.3 line status register ................................ ................................ ................................ ... 61 5.4 interrupt identification register ................................ ................................ ................... 62 5.5 interrupt enable register ................................ ................................ ............................ 63 5.6 fifo control register ................................ ................................ ................................ . 63 5.7 modem control register ................................ ................................ ............................. 64 5.8 modem status register ................................ ................................ .............................. 65 5.9 scratchpad register ................................ ................................ ................................ ... 65 5.10 infrared interface ................................ ................................ ................................ ....... 65 section 6 : keyboard controller and real time clock functional description ........................ 66 6.1 keyboard and rtc lsa interface ................................ ................................ ................ 66 6.2 keyboard controller ................................ ................................ ................................ .... 66 6.3 real time clock ................................ ................................ ................................ ......... 73 section 7 : bios ................................ ................................ ................................ .......................... 79 7.1 bios buffer ................................ ................................ ................................ ................ 79 section 8 : parallel port ................................ ................................ ................................ .............. 80 8.1 parallel por t interface ................................ ................................ ................................ . 80 8.2 ibm xt/at compatible, bi-directional and epp modes ................................ ................ 81 section 9 : common i/o ports ................................ ................................ ................................ .... 95 section 10 : electrical characteristics ................................ ................................ ....................... 99 10.1 absolute maximum ratings ................................ ................................ ........................ 99 10.2 dc characteristics ................................ ................................ ................................ ...... 99 10.3 ac characteristics ................................ ................................ ................................ ...... 101 10.4 ac test conditions ................................ ................................ ................................ ..... 102 section 11 : packaging information ................................ ................................ ........................... 120 section 12 : ordering information ................................ ................................ .............................. 121 section 13 : revision history ................................ ................................ ................................ ..... 122 worldwide distributors and sales offices ................................ ................................ ................. 123
acer laboratories inc. --preliminary, confidential, proprietary-- m512x : mega i/o controller with pnp 07-02-1997 document number: 512xds02.doc page 3 acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, r.o.c. tel: 886-(02) 762-8800 fax: 762-6060 section 1 : introduction features and functions the acer labs' m512x chip has two full-function universal asynchronous receiver/ transmitters (uarts), a keyboard interface, real time clock, a floppy disk controller (fdc) with data separator, parallel port, standard xt/at address decoding for on-chip functions, and a configuration register. it offers a single-chip solution to the most common ibm pc, xt, at and notebook peripherals. the floppy disk controller is fully compatible with the industry-standard 765a and 82077sl architecture. it includes more advanced options such as a high performance data separator, extended track range to 4096, high performance power management, implied seek command, scan command, and supports both ibm and iso 360k/1.2m/720k/1.44m/2.88m fdd formats. the uarts are compatible with either the ins8250n-b, ns16450 and 16550. it has complete compatibility with the ibm at's parallel port. the configuration register is one-byte wide and can be programmed via hardware or software. by controlling this register, the user can assign standard at addresses and disable any major on-chip function (e.g., the fdc, either uart, or the parallel port) independent of the others. this allows for flexibility in system configuration when adapter boards contain duplicate functions. the m512x provides support for the isa plug-and-play standard and recommended functionality to support windows ? 95. through internal configuration registers, each of the m512x ? s logic device ? s i/o address, dma channel and irq channel may be programmed. there are 96 i/o address location options, 13 irq options, and three dma channel options for each logical device except kbc and rtc. kbc ? s i/o address is not routable. rtc ? s i/o address and irq are not routable as well. 1.2 m512x block diagrams the following figures show the overall block diagram of the m512x.
--preliminary, confidential, proprietary-- acer laboratories inc. m512x : mega i/o controller with pnp page 4 07-02-1997 document number: 512xds02.doc acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, roc tel: 886-(02) 762-8800 fax: 762-6060 rdataj wgatej wdataj hdselj dirj stepj dskchgj drv0-1 pdir mot0-1 wpj trk0j densel indexj ali m512x isa bus interface floppy disk interface serial port 1 serial port 2 kbc rtc printer port interface sd0-sd7 iorj iowj aen sa0-sa15 dack0j-dack3j drq0-drq3 tc irq1,irq3-12,irq14-15 mr sin1, sout1 rts1j dtr1j cts1j dsr1j dcd1j ri1j sin2,sout2 rts2j dtr2j cts2j dsr2j dcd2j ri2j autofdj initj slctinj strobej busy ackj pe slct errorj iochrdy pd0-pd7 xtal1,2 vbat pwg kdat,kclk mdat,mclk bios buffer common i/o romoej romcsj rd0-7 cio 10-17,20-25,30-34 figure 1-1 m512x block diagram
acer laboratories inc. --preliminary, confidential, proprietary-- m512x : mega i/o controller with pnp 07-02-1997 document number: 512xds02.doc page 5 acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, r.o.c. tel: 886-(02) 762-8800 fax: 762-6060 1.3 register overview table 1-1 i/o address decode address range block name logical device function base + (0-5) and + (7) floppy disk 0 base + (0-7) serial port com1 4 ir support base + (0-7) serial port com2 5 ir support base + (0-3) base + (0-7) base + (0-3), + (400-402) base + (0-7), + (400-402) parallel port spp epp ecp ecp+epp+spp 3 0x60, 0x64 0x70, 0x71 kbc rtc 7 6
--preliminary, confidential, proprietary-- acer laboratories inc. m512x : mega i/o controller with pnp page 6 07-02-1997 document number: 512xds02.doc acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, roc tel: 886-(02) 762-8800 fax: 762-6060 section 2 : pin description 2.1 pinout diagram pwg romcsj rd7 rd6 rd5 rd4 rd3 rd2 rd1 rd0 cio25 cio24 cio23 cio22 cio21 cio20 cio17/i2c_dat cio16/i2c_clk cio15/p20 vdd cio14/p21 cio13/irtx cio12/irrx cio11/irqin2 cio10/irqin1 gnd mclk mdat kclk kdat iochrdy tc drq3 dack3j drq2 dack2j drq1 dack1j drq0 dack0j gnd drvden0 drvden1 mot0j drv1j drv0j mot1j gnd dirj stepj wdataj wgatej hdselj indexj trk0j wprotj rdataj dskchgj mid1 mid0 vdd 14clki cio30/kbcclk cio31/cs0j cio32/cs1j pdir/ps2drv sa[13] sa[14] sa[15] cio33/alt_kclk cio34/alt_kdat cio35/alt_mclk cio36/alt_mdat cio37/alt_kbc x24tal1 x24tal2 clk01 clk02 romoej gnd 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 ali m512x figure 2-1. m512x pin diagram
acer laboratories inc. --preliminary, confidential, proprietary-- m512x : mega i/o controller with pnp 07-02-1997 document number: 512xds02.doc page 7 acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, r.o.c. tel: 886-(02) 762-8800 fax: 762-6060 2.2 pin description table 2-1 lists the functions of all m512x pins. a low represents a logic 0 (0v nominal) and a high represents a logic 1 (+2.4v nominal). table 2-1 m512x pin descript ion table name number type description host processor interface sd0-sd7 70-72 i/o data bus . these signals are used by the host microprocessor to transmit data to and from the m512x. these pins are in high impedance state when not in the output mode. iorj 68 i i/o read . this active low signal is issued by the host microprocessor to indicate a read operation. iowj 69 i i/o write . this active low signal is issued by the host microprocessor to indicate a write operation. aen 70 i address enable . this active high signal indicates dma operations on the host data bus. sa0-sa15 41-53, 27-29 i i/o address . these bits determine the i/o address to be accessed during iorj and iowj cycles. dack0j- dack3j 81,83,85,87 i dma acknowledge. an active low input signal acknowledging the request for a dma data transfer. this input enables the dma read or write internally. drq0- drq3 82,84,86,88 o dma request . this active high output is the dma request for byte transfers of data to the host. this signal is cleared on the last byte of the data transfer by the dackj signal going low. tc 89 i terminal count . this signal indicates to the m512x that data transfer is complete. tc is only accepted when dackj is low. tc is active high in at mode and active low in ps/2 mode. irq1, irq3-12, irq14-15 67,66,65,64, 63,62,61,59, 58,57,56,55, 54 o interrupt requests . mr 80 is reset . this active high signal resets the m512x and must be valid for 500 ns minimum. in m512x, the falling edge of reset latches the jumper configuration. the jumper select lines must be valid 50 ns prior to this edge. floppy disk interface rdataj 17 is read disk data. this raw data read signal from the disk is connected here. each falling edge represents a flux transition of the encoded data. wgatej 12 o write gate . this active-low, high-drive output enables the write circuitry of the selected disk drive. this signal prevents glitches during power-up and power- down. unstable power prevents writing to the disk. wdataj 11 o write data . this active low output is a write- precompensated serial data to be written onto the selected disk drive. each falling edge causes a flux change on the media. hdselj 13 o head select . this active low output determines which disk drive head is active. low = head 0, high (open) = head 1. dirj 9 o direction. this active low output determines the direction of the head movement (low = step-in, high = step-out). during write or read modes, this output is high. stepj 10 o step. this active low signal produces a pulse to move the head during a seek operation. dskchgj 18 is disk change. this disk interface signal indicates when the disk drive door is open. this signal is read from bit d7 of address xx7h.
--preliminary, confidential, proprietary-- acer laboratories inc. m512x : mega i/o controller with pnp page 8 07-02-1997 document number: 512xds02.doc acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, roc tel: 886-(02) 762-8800 fax: 762-6060 table 2-1 m512x pin description table (continued) name number type description floppy disk interface : drv0j, drv1j 6, 5 o drive select 0, 1 . active low, output select drives 0-1. pdir ps2drv 26 o i this bit is used to indicate the direction of the parallel port data bus. 0= output/write, 1= input / read. drive 2 . in ps/2 mode, this input indicates whether a second drive is connected; this signal should be low if a second drive is connected. this status is reflected in a read of status register a. mid0-1 20,19 is media id inputs. in floppy enhanced mode, these inputs are the media id inputs. mot0j, mot1j 4, 7 o motor on 0, 1 . these active-low outputs select motor drives 0-1. wprotj 16 is write protected . this active-low schmitt trigger input senses from the disk drive that a disk is write-protected. any write command is ignored. trk0j 15 is track 00 . this schmitt trigger input signal senses from the disk drive that the head is positioned over the outermost track. indexj 14 is index . this active low schmitt trigger input senses from the disk drive that the head is positioned over the beginning of a track, as marked by an index hole. drvden 0-1 2-3 o data rate 0-1 . this output reflects bits 0-1 of the data rate register. serial port interface : sin1, sin2 145,155 i receive data . receiver serial data input. sout1, sout2 146,156 o transmit data . transmitter serial data output from serial port. rts1j cfgport 148 o i request to send . active low request to send output for primary serial port. handshake output signal notifies modem that the uart is ready to transmit data. this signal can be programmed by writing to bit 1 of modem control register (mcr). the hardware reset will clear the rtsj signal to inactive mode (high). forced inactive during loop mode operation. configuration port select . during reset active, this input is read and latched to define the configuration register ? s base address. rts2j kbc_en 158 o i request to send . this active low signal for secondary serial port. handshake output signal notifies modem that the uart is ready to transmit data. this signal can be programmed by writing to bit 1 of modem control register (mcr). the hardware reset will clear the rtsj signal to inactive mode (high). forced inactive during loop mode operation. kbc enable control . during reset active, this input is read and latched to enable kbc after reset. the signal can be overwritten by configuration register. dtr1j rtc_en 150 o i data terminal ready . this is an active low output for primary serial port. handshake output signal signifies to modem that the uart is ready to establish data communication link. this signal can be programmed by writing to bit 0 of modem control register (mcr). the hardware reset will clear the dtrj signal to inactive during loop mode operation. rtc enable control . during reset active, this input is read and latched to enable rtc after reset. this signal can be overwritten by configuration register.
acer laboratories inc. --preliminary, confidential, proprietary-- m512x : mega i/o controller with pnp 07-02-1997 document number: 512xds02.doc page 9 acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, r.o.c. tel: 886-(02) 762-8800 fax: 762-6060 table 2-1 m512x pin description table (continued) name number type description serial port interface : dtr2j ps2_atj 160 o i data terminal ready . this active low output is for secondary serial port. handshake output signal notifies modem that the uart is ready to establish data communication link. this signal can be programmed by writing to bit 0 of modem control register (mcr). the hardware reset will clear the dtrj signal to inactive mode (high). forced inactive during loop mode operation. kbc ps2 mode or at mode select . when active, this input is read and latched to define the kbc ps-2 or at mode. cts1j cts2j 149, 159 i clear to send . this active low input for primary and secondary serial ports. handshake signal which notifies the uart that the modem is ready to receive data. the cpu can monitor the status of ctsj signal by reading bit 4 of modem status register (msr). a ctsj signal state is directly comparative with the msr bit after the last msr read. if bit 3 of interrupt enable register is set, the interrupt is generated when ctsj changes state. the ctsj signal has no effect on the transmitter. note : bit 4 of msr is the complement of ctsj. dsr1j dsr2j 147, 157 i data set ready. this active low input is for primary and secondary serial ports. handshake signal which notifies the uart that the modem is ready to establish the communication link. the cpu can monitor the status of dsrj signal by reading bit5 of modem status register (msr). a dsrj signal state change from low to high after the last msr read will raise the msr bit 1. if bit 3 of interrupt enable register is set, the interrupt is generated when dsrj changes state. note: bit 5 of msr is the complement of dsrj. dcd1j, dcd2j 152, 154 i data carrier detect . this active low input is for primary and secondary serial ports. handshake signal which notifies the uart that carrier signal is detected by the modem. the cpu can monitor the status of dcdj signal by reading bit 7 of modem status register (msr). a dcdj signal state rises after the last msr read will raise msr bit 3. if bit 3 of interrupt enable register is set, the interrupt is generated when dcdj changes state. note : bit 7 of msr is the complement of dcdj. ri1j, ri2j 151, 153 i ring indicator . this active low input is for primary and secondary serial ports. handshake signal that notifies the uart that the telephone ring signal is detected by the modem. the cpu can monitor the status of rij signal by reading bit 6 of modem status register (msr). a risen rij signal state after the last msr read will raise msr bit 2 to a 1. if bit 3 of interrupt enable register is set, the interrupt is generated when rij changes state. note : bit 6 of msr is the complement of rij.
--preliminary, confidential, proprietary-- acer laboratories inc. m512x : mega i/o controller with pnp page 10 07-02-1997 document number: 512xds02.doc acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, roc tel: 886-(02) 762-8800 fax: 762-6060 table 2-1 m512x pin description table (continued) name number type description printer port interface autofdj 143 o autofeed output . this active low output causes the printer to automatically feed one line after each line is printed. this signal is the complement of bit 1 of the printer control register. initj 141 o initiate output . this active low signal is bit 2 of the printer control register. this signal is used to initialize the printer. slctinj 140 o printer select input . this active low signal selects the printer. this is the complement of bit 3 of the printer control register. strobej 144 o strobe output . this active low pulse is used to strobe the printer data into the printer. this output signal is the complement of bit 0 of the printer control register. busy 128 is busy . this signal indicates the status of the printer. a high indicates the printer is busy and not ready to receive new data. bit 7 of the printer status register is the complement of the busy input. ackj 129 is acknowledge . this active low signal from the printer indicates it has received the data and is ready to accept new data. bit 6 of the printer status register reads the ackj input. pe 127 is paper end . this signal indicates that the printer is out of paper. bit 5 of the printer status register reads the pe input. slct 126 is printer selected status . this active high signal from the printer indicates that it has power on. bit 4 of the printer status register reads the slct input. errorj 142 i error . this active low signal indicates an error condition at the printer. pd0-pd7 138-131 i/o port data . this bi-directional parallel data bus is used to transfer information between cpu and peripherals. iochrdy 90 od iochrdy . in epp mode, this pin is pulled low to extend the read/write command. real-time clock xtal1 122 iclk 32khz crystal input . xtal2 124 oclk 32khz crystal output . vbat 121 p battery voltage. pwg 120 is power good input. keyboard controller kdat 91 i/o keyboard data. kclk 92 i/o keyboard clock. mdat 93 i/o mouse data. mclk 94 i/o mouse clock.
acer laboratories inc. --preliminary, confidential, proprietary-- m512x : mega i/o controller with pnp 07-02-1997 document number: 512xds02.doc page 11 acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, r.o.c. tel: 886-(02) 762-8800 fax: 762-6060 table 2-1 m512x pin description table (continued) name number type description bios buffer : romoej 39 is rom output enable. romcsj 119 is rom chip select. rd0-7 111-118 i/o rom bus. common i/o : cio10-11 96-97 i/o i common i/o pin. irq in. cio12 98 i/o i common i/o pin. irrx. cio13 99 i/o o common i/o pin. irtx. cio14 100 i/o o common i/o pin. kbc p21 function. cio15 102 i/o o common i/o pin. kbc p20 function. cio16 103 i/o o common i/o pin. i 2 c_clk. cio17 104 i/o i/o common i/o pin. i 2 c_dat. cio20-24 105-109 i/o common i/o pin. cio25 110 i/o i common i/o pin. keylockj. cio30 23 i/o i common i/o pin. kbc_clk. cio31 24 i/o o common i/o pin. general chip select decoder cs0j. cio32 25 i/o o common i/o pin. general chip select decoder cs1j. cio33 30 i/o o common i/o pin. alternative keyboard clock. cio34 31 i/o o common i/o pin. alternative keyboard data. cio35 32 i/o o common i/o pin. alternative mouse clock. cio36 33 i/o o common i/o pin. alternative mouse data. cio37 34 i/o i common i/o pin. alternative kbc select.
--preliminary, confidential, proprietary-- acer laboratories inc. m512x : mega i/o controller with pnp page 12 07-02-1997 document number: 512xds02.doc acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, roc tel: 886-(02) 762-8800 fax: 762-6060 table 2-1 m512x pin description table (continued) name number type description miscellaneous x24tal1 35 iclk clock 1 . this is an external connection for a parallel resonant 24 mhz crystal. a cmos compatible oscillator is required if crystal is not used. x24tal2 36 oclk clock 2 . this is a 24 mhz crystal. if an external clock is used, this pin should not be connected. this pin should not be used to drive any other drivers. x14clki 22 i clock 14 in . this is a 14.318 mhz clock source in. xclko1 37 o clock 14 out . this is a 14.318 mhz clock out. xclko2 38 o clock 14 out . this is the second 14.318 mhz clock out. power pins vcc 21,60,101, 125,139 p power . +5 volt supply pin. vss 1,8,40,71,95, 123,130 p ground pins . type description : i input ttl compatible. is input with schmitt trigger. iclk clk input. oclk clk output. o4 output with 4 ma sink @ 0.4 v, source 4 ma @ 2.4 v. od24 open drain outputs, sinks 24 ma @ 0.4 v.
acer laboratories inc. --preliminary, confidential, proprietary-- m512x : mega i/o controller with pnp 07-02-1997 document number: 512xds02.doc page 13 acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, r.o.c. tel: 886-(02) 762-8800 fax: 762-6060 2.3 numerical pin list pin no. pin name type 1 vss p 2 drvden0 o 3 drvden1 o 4 mot0j o 5 drv1j o 6 drv0j o 7 mot1j o 8 vss p 9 dirj o 10 stepj o 11 wdataj o 12 wgatej o 13 hdselj o 14 indexj is 15 trk0j is 16 wprotj is 17 rdataj is 18 dskchgj is 19 mid1 is 20 mid0 is 21 vcc p 22 x14clki i 23 cio30/ kbc_clk i/o 24 cio31/cs0j i/o 25 cio32/cs1j i/o 26 pdir/ps2drv i/o 27 sa13 is 28 sa14 is 29 sa15 is 30 cio33/ alt_kclk i/o 31 cio34/ alt_kdat i/o 32 cio35/ alt_mclk i/o 33 cio36/ alt_mdat i/o 34 cio37/ alt_kbc i/o 35 x24tal1 iclk 36 x24tal2 oclk 37 xclko1 o 38 xclko2 o 39 romoej is 40 vss p pin no. pin name type 41 sa0 is 42 sa1 is 43 sa2 is 44 sa3 is 45 sa4 is 46 sa5 is 47 sa6 is 48 sa7 is 49 sa8 is 50 sa9 is 51 sa10 is 52 sa11 is 53 sa12 is 54 irq15 o 55 irq14 o 56 irq12 o 57 irq11 o 58 irq10 o 59 irq9 o 60 vcc p 61 irq8 o 62 irq7 o 63 irq6 o 64 irq5 o 65 irq4 o 66 irq3 o 67 irq1 o 68 iorj is 69 iowj is 70 aen is 71 vss p 72 sd0 i/o 73 sd1 i/o 74 sd2 i/o 75 sd3 i/o 76 sd4 i/o 77 sd5 i/o 78 sd6 i/o 79 sd7 i/o 80 mr is
--preliminary, confidential, proprietary-- acer laboratories inc. m512x : mega i/o controller with pnp page 14 07-02-1997 document number: 512xds02.doc acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, roc tel: 886-(02) 762-8800 fax: 762-6060 numerical pin list (continued) pin no. pin name type 81 dack0j is 82 drq0 o 83 dack1j is 84 drq1 o 85 dack2j is 86 drq2 o 87 dack3j is 88 drq3 o 89 tc is 90 iochrdy od 91 kdat i/o 92 kclk i/o 93 mdat i/o 94 mclk i/o 95 vss p 96 cio10/irqin1 i/o 97 cio11/irqin2 i/o 98 cio12/irrx i/o 99 cio13/irtx i/o 100 cio14/ga20 i/o 101 vcc p 102 cio15/kbrcj i/o 103 cio16/i 2 c_clk i/o 104 cio17/i 2 c_dat i/o 105 cio20 i/o 106 cio21 i/o 107 cio22 i/o 108 cio23 i/o 109 cio24 i/o 110 cio25 i/o 111 rd0 i/o 112 rd1 i/o 113 rd2 i/o 114 rd3 i/o 115 rd4 i/o 116 rd5 i/o 117 rd6 i/o 118 rd7 i/o 119 romcsj is 120 pwg is pin no. pin name type 121 vbat p 122 x32tal1 iclk 123 vss p 124 x32tal2 oclk 125 vcc p 126 slct is 127 pe is 128 busy is 129 ackj is 130 vss p 131 pd7 i/o 132 pd6 i/o 133 pd5 i/o 134 pd4 i/o 135 pd3 i/o 136 pd2 i/o 137 pd1 i/o 138 pd0 i/o 139 vcc p 140 slctinj o 141 initj o 142 errorj i 143 autofdj o 144 strobj o 145 sin1 is 146 sout1 o 147 dsr1j is 148 rts1j/ cfg_port i/o 149 cts1j is 150 dtr1j/rtc_en i/o 151 ri1j is 152 dcd1j is 153 ri2j is 154 dcd2j is 155 sin2 is 156 sout2 o 157 dsr2j is 158 rts2j/kbc_en i/o 159 cts2j is 160 dtr2j/ps2_atj i/o
acer laboratories inc. --preliminary, confidential, proprietary-- m512x : mega i/o controller with pnp 07-02-1997 document number: 512xds02.doc page 15 acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, r.o.c. tel: 886-(02) 762-8800 fax: 762-6060 2.4 alphabetical pin list pin no. pin name type 129 ackj is 70 aen is 143 autofdj o 128 busy is 96 cio10/irqin1 i/o 97 cio11/irqin2 i/o 98 cio12/irrx i/o 99 cio13/irtx i/o 100 cio14/ga20 i/o 102 cio15/kbrcj i/o 103 cio16/i 2 c_clk i/o 104 cio17/i 2 c_dat i/o 105 cio20 i/o 106 cio21 i/o 107 cio22 i/o 108 cio23 i/o 109 cio24 i/o 110 cio25 i/o 23 cio30/kbc_clk i/o 24 cio31/cs0j i/o 25 cio32/cs1j i/o 30 cio33/alt_kclk i/o 31 cio34/alt_kdat i/o 32 cio35/alt_mclk i/o 33 cio36/alt_mdat i/o 34 cio37/alt_kbc i/o 149 cts1j is 159 cts2j is 81 dack0j is 83 dack1j is 85 dack2j is 87 dack3j is 152 dcd1j is 154 dcd2j is 9 dirj o 82 drq0 o 84 drq1 o 86 drq2 o 88 drq3 o 2 drvden0 o pin no. pin name type 3 drvden1 o 5 drv1j o 6 drv0j o 18 dskchgj is 147 dsr1j is 157 dsr2j is 150 dtr1j/rtc_en i/o 160 dtr2j/ps2_atj i/o 142 errorj i 13 hdselj o 14 indexj is 141 initj o 90 iochrdy od 68 iorj is 69 iowj is 67 irq1 o 66 irq3 o 65 irq4 o 64 irq5 o 63 irq6 o 62 irq7 o 61 irq8 o 59 irq9 o 58 irq10 o 57 irq11 o 56 irq12 o 55 irq14 o 54 irq15 o 91 kdat i/o 92 kclk i/o 94 mclk i/o 93 mdat i/o 19 mid1 is 20 mid0 is 4 mot0j o 7 mot1j o 80 mr is 138 pd0 i/o 137 pd1 i/o 136 pd2 i/o
--preliminary, confidential, proprietary-- acer laboratories inc. m512x : mega i/o controller with pnp page 16 07-02-1997 document number: 512xds02.doc acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, roc tel: 886-(02) 762-8800 fax: 762-6060 alphabetical pin list (continued) pin no. pin name type 135 pd3 i/o 134 pd4 i/o 133 pd5 i/o 132 pd6 i/o 131 pd7 i/o 26 pdir/ps2drv i/o 127 pe is 120 pwg is 111 rd0 i/o 112 rd1 i/o 113 rd2 i/o 114 rd3 i/o 115 rd4 i/o 116 rd5 i/o 117 rd6 i/o 118 rd7 i/o 17 rdataj is 151 ri1j is 153 ri2j is 119 romcsj is 39 romoej is 148 rts1j/cfg_port i/o 158 rts2j/kbc_en i/o 41 sa0 is 42 sa1 is 43 sa2 is 44 sa3 is 45 sa4 is 46 sa5 is 47 sa6 is 48 sa7 is 49 sa8 is 50 sa9 is 51 sa10 is 52 sa11 is 53 sa12 is 27 sa13 is 28 sa14 is 29 sa15 is 72 sd0 i/o pin no. pin name type 73 sd1 i/o 74 sd2 i/o 75 sd3 i/o 76 sd4 i/o 77 sd5 i/o 78 sd6 i/o 79 sd7 i/o 145 sin1 is 155 sin2 is 140 slctinj o 126 slct is 146 sout1 o 156 sout2 o 10 stepj o 144 strobj o 89 tc is 15 trk0j is 121 vbat p 21 vcc p 60 vcc p 101 vcc p 125 vcc p 139 vcc p 1 vss p 8 vss p 40 vss p 71 vss p 95 vss p 123 vss p 130 vss p 11 wdataj o 16 wprotj is 12 wgatej o 22 x14clki i 35 x24tal1 iclk 36 x24tal2 oclk 122 x32tal1 iclk 124 x32tal2 oclk 37 xclko1 o 38 xclko2 o
acer laboratories inc. --preliminary, confidential, proprietary-- m512x : mega i/o controller with pnp 07-02-1997 document number: 512xds02.doc page 17 acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, r.o.c. tel: 886-(02) 762-8800 fax: 762-6060 section 3 : configuration description and power management features 3.1 configuration port this configuration is based on the typical plug-and-play architecture and allows the bios to assign resources at post. to assign m512x a configuration key, <0x51, 0x23> must be written to config port to enter the configure mode. then follow the plug-and-play procedure to configure each device. a configuration key = < 0xbb > must be written to config port to exit the configure mode and enter the run mode. note : after exiting the configure mode, the current logic device select is cleared. you must select the logic device before you program it. after a hard reset or power on reset, the m512x is in the run mode with all logical devices disable except kbc and rtc. the hardware setting pins control the kbc and rtc. then the normal configure procedure is also suitable for kbc and rtc. the hardware setting is listed on table 3-2. all logical devices may be configured through 2 standard configuration i/o ports ( index and data ) by placing the m512x into configuration mode. the bios uses these configuration ports to initialize the logical devices at post. the index and data ports are only valid when the m512x is in configuration mode. a hardware setting pin cfg_port is latched to select the cfg_port as 3f0h or 370h. port name cfg_port=0 cfg_port=1 type config port 0x3f0 0x370 w index port 0x3f0 0x370 w data port 0x3f1 0x371 r/w chip level registers index name hard reset, soft reset default values index 0x02h 0x00, 0x00 bit 0 1 : soft reset the configuration registers. this bit is automatically cleared after write. this register is write only. index 0x03h 0x03, n/a bit 1-0 set cio1, cio2, and cio3 selection register address. 00 : 0xe0 01 : 0xe2 10 : 0xe4 11 : 0xea bit 7 0 : disable access 1 : enable access to cio1, cio2, and cio3. index 0x07h 0x00, 0x00 bit 3-0 select the current logic device. this allows the access to each logical device ? s registers. bit 7-4 read as 0. index 0x20h 0x23, 0x23 ali defined device identification. read only. index 0x21h 0x51, 0x51 ali defined device identification. read only.
--preliminary, confidential, proprietary-- acer laboratories inc. m512x : mega i/o controller with pnp page 18 07-02-1997 document number: 512xds02.doc acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, roc tel: 886-(02) 762-8800 fax: 762-6060 index 0x22h 0x00, 0x00 bit 0 direct powerdown fdc (note 3) 0 : disable 1 : enable bit 2-1 read as 0. bit 3 direct powerdown parallel port (note 3) 0 : disable 1 : enable bit 4 direct powerdown uart1 (note 3) 0 : dis able 1 : enable bit 5 direct powerdown uart2 (note 3) 0 : disable 1 : enable bit 6 1: turn off the oscillator. bit 7 read as 0. index 0x23h 0x00, n/a bit 2-0 read as 0. bit 3 auto powerdown parallel port. 0 : disable 1 : enable bit 4 auto powerdown uart1. 0 : disable 1 : enable bit 5 auto powerdown uart2. 0 : disable 1 : enable bit 7-6 read as 0 index 0x24h 0x00, n/a bit 5-0 read as 0. bit 6 0 : pin26 functions as pdir 1 : pin26 functions as sdrv. bit 7 0 : irq8 is active high 1 : irq8 is active low.(note 1) index 0x2dh 0x00, n/a reserved for test purposes only logical device 0 registers (fdc) index 0x30h 0x00, 0x00 bit 0 fdc (note 4) 0 : disable 1 : enable bit 7-1 read as 0. index 0x60h 0x03, 0x03 the higher address of the fdc ? s i/o base address. bit 7-2 read as 0. index 0x61h 0xf0, 0xf0 the lower address of the fdc ? s i/o base address. bit 2-0 set to 0.
acer laboratories inc. --preliminary, confidential, proprietary-- m512x : mega i/o controller with pnp 07-02-1997 document number: 512xds02.doc page 19 acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, r.o.c. tel: 886-(02) 762-8800 fax: 762-6060 index 0x70h 0x06, 0x06 bit 3-0 select irq channel used by fdc. 0000 : none 0001 : irq1 0010 : n/a 0011 : irq3 0100 : irq4 0101 : irq5 0110 : irq6 0111 : irq7 1000 : n/a 1001 : irq9 1010 : irq10 1011 : irq11 1100 : irq12 1101 : n/a 1110 : irq14 1111 : irq15 bit 7-4 read as 0. index 0x74h 0x02, 0x02 bit 2-0 select dma channel used by fdc 000 : dma0 001 : dma1 010 : dma2 011 : dma3 100 : none bit 7-3 read as 0. index 0xf0h 0x08, n/a bit 0 0 : normal mode 1 : enhanced os2 mode bit 1 0 : burst dma mode. 1 : non-bu rst dma mode bit 2, 7-5 read as 0. bit 3 0 : ps2 mode 1 : at mode bit 4 0 : no swap. 1 : swap drive 0 and drive 1 index 0xf1h 0x00, n/a bit 1-0 external floppy select. 0x : internal fdc 10 : external fdc 11 : drive a internal, drive b external bit 3-2 density select. 0x : normal 10 : force to 1 11 : force to 0 bit 5-4 media id[1-0] polarity. 0 : normal 1 : inverted bit 7-6 boot floppy. 00 : fdd 0 01 : fdd 1 10 : fdd 2 11 : fdd 3 index 0xf2h 0xff, n/a bit 1-0 floppy drive a type. bit 3-2 floppy drive b type. bit 5-4 floppy drive c type. bit 7-6 floppy drive d type. index 0xf4h 0x00, n/a bit 1-0 drvden[1-0] signal definition (refer to table 3-4). bit 2, 7-5 read as 0. bit 4-3 data rate table select (refer to table 3-3).
--preliminary, confidential, proprietary-- acer laboratories inc. m512x : mega i/o controller with pnp page 20 07-02-1997 document number: 512xds02.doc acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, roc tel: 886-(02) 762-8800 fax: 762-6060 logical device 3 registers (parallel port) index 0x30h 0x00, 0x00 bit 0 activate parallel port. (note 4) 0 : disable 1 : enable bit 7-1 read as 0. index 0x60h 0x03, 0x03 the higher address of the parallel port ? s i /o base address. bit 7-2 read as 0. index 0x61h 0x78, 0x78 the lower address of the parallel port ? s i/o base address. bit 1-0 set to 0. note : an 8-byte boundary is required if epp is available index 0x70h 0x05, 0x05 bit 3-0 select irq channel used by parallel port. 0000 : none 0001 : irq1 0010 : n/a 0011 : irq3 0100 : irq4 0101 : irq5 0110 : irq6 0111 : irq7 1000 : n/a 1001 : irq9 1010 : irq10 1011 : irq11 1100 : irq12 1101 : n/a 1110 : irq14 1111 : irq15 bit 7-4 read as 0. index 0x74h 0x04, 0x04 bit 2-0 select dma channel used by parallel port. 000 : dma0 001 : dma1 010 : dma2 011 : dma3 100 : none bit 7-3 read as 0. index 0xf0h 0xbc, n/a bit 2-0 epp compatible mode. 000 : ps2 001 : epp 1.9 010 : ecp 011 : ecp+epp1.9 100 : spp 101 : epp 1.7 111 : ecp+epp 1.7 bit 6-3 ecp fifo threshold value. default is 0001. bit 7 pp interrupt type (not valid when pp is in spp or ps2 mode). 1 : irq active low. 0 : irq active high . index 0xf1h 0x05, n/a bit 0 0 : non-burst dma mode. 1 : burst dma transfer mode in ecp bit 1 epp time-out interrupt. 0 : disable 1 : enable bit 2 pp operation clock. 0 : 24 mhz. 1 : 12 mhz bit 7-3 read as 0.
acer laboratories inc. --preliminary, confidential, proprietary-- m512x : mega i/o controller with pnp 07-02-1997 document number: 512xds02.doc page 21 acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, r.o.c. tel: 886-(02) 762-8800 fax: 762-6060 logical device 4 registers (uart1) index 0x30h 0x00, 0x00 bit 0 uart1 (note 4) 0 : disable 1 : enable bit 7-1 read as 0. index 0x60h 0x03, 0x03 the higher address of the uart1 ? s i/o base address. bit 7-2 read as 0. index 0x61h 0xf8, 0xf8 the lower address of the uart1 ? s i/o base address. bit 2-0 is set to 0. index 0x70h 0x04, 0x04 bit 3-0 select irq used by uart1. 0000 : none 0001 : irq1 0010 : n/a 0011 : irq3 0100 : irq4 0101 : irq5 0110 : irq6 0111 : irq7 1000 : n/a 1001 : irq9 1010 : irq10 1011 : irq11 1100 : irq12 1101 : n/a 1110 : irq14 1111 : irq15 bit 7-4 read as 0. index 0xf0h 0x00, n/a bit 0 midi support 0 : disable 1 : enable bit 1 high speed mode 0 : disable 1 : enable bit 2 0 : normal 1 : 8mhz clock source for uart1 bit 7-3 read as 0. index 0xf1h 0x00, n/a bit 0 ir receive polarity. 0 : active high 1 : active low bit 1 ir transmit polarity. 0 : active high 1 : active low bit 2 0 : full duplex in ir 1 : half duplex in ir bit 4-3 ir mode. 00 : normal 01 : irda 10 : ask ir 11 : normal bit 7-5 read as 0. index 0xf2h 0x0c, n/a bit 0 baud rate output on ri1. 0 : disable 1 : enable bit 1 ir half-duplex tx-to-rx time- out timer. 0 : disable 1 : enable bit 2 ir half-duplex rx-to-tx time-out timer. 0 : disable 1 : enable bit 4-3 ir half-duplex time-out time control. 00: 41-bit time for tr, 39-bit time for rx. 01: 42-bit time for tr, 39-bit time for rx 1x: 40-bit time for tr and rx bit 7-5 read as 0.
--preliminary, confidential, proprietary-- acer laboratories inc. m512x : mega i/o controller with pnp page 22 07-02-1997 document number: 512xds02.doc acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, roc tel: 886-(02) 762-8800 fax: 762-6060 logical device 5 registers (uart2) index 0x30h 0x00, 0x00 bit 0 uart2 (note 4) 0 : disable 1 : enable bit 7-1 read as 0. index 0x60h 0x02, 0x02 the higher address of the uart2 ? s i/o base address. bit 7-2 read as 0. index 0x61h 0 xf8, 0xf8 the lower address of the uart2 ? s i/o base address. bit 2-0 set to 0. index 0x70h 0x03, 0x03 bit 3-0 select irq channel used by uart2. 0000 : none 0001 : irq1 0010 : n/a 0011 : irq3 0100 : irq4 0101 : irq5 0110 : irq6 0111 : irq7 1000 : n/a 1001 : irq9 1010 : irq10 1011 : irq11 1100 : irq12 1101 : n/a 1110 : irq14 1111 : irq15 bit 7-4 read as 0. index 0xf0h 0x00, n/a bit 0 midi support 0 : disable 1 : enable bit 1 high speed mode 0 : disabl e 1 : enable bit 2 1 : 8 mhz clock source for uart2 0 : normal bit 7-3 read as 0. index 0xf1h 0x02, n/a bit 0 ir receive polarity. 0 : active high 1 : active low bit 1 ir transmit polarity. 0: active high 1: active low bit 2 1 : half duplex in ir 0 : full duplex in ir. bit 4-3 ir mode. 00 : normal 01 : irda 10 : ask ir 11 : normal bit 5, 7 read as 0. bit 6 ir input source. 0 : use tx2 and rx2 1 : use irrx2 and irtx2
acer laboratories inc. --preliminary, confidential, proprietary-- m512x : mega i/o controller with pnp 07-02-1997 document number: 512xds02.doc page 23 acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, r.o.c. tel: 886-(02) 762-8800 fax: 762-6060 index 0xf2h 0x0c, n/a bit 0 baud rate out put on ri2 0 : disable 1 : enable bit 1 ir half-duplex tx-to-rx time-out timer. 0 : disable 1 : enable bit 2 ir half-duplex rx-to-tx time-out timer 0 : disable 1 : enable bit 4-3 ir half-duplex time-out time control. 1x : 40-bit time for tr and rx 01 : 42-bit time for tr, 39-bit time for rx 00 : 41-bit time for tr, 39-bit time for rx. bit 7-5 read as 0. logical device 6 registers (rtc) index 0x30h 0x00, 0x00 bit 0 0 : deactivate rtc (note 4) 1 : activate rtc. this is a hardware setting bit by dtr1j. bit 7-1 read as 0. index 0xf0h 0x00, n/a bit 0 cmos ram 0x80-0x9f 0 : unlock 1 : lock bit 1 cmos ram 0xa0-0xbf. 0 : unlock 1 : lock bit 2 cmos ram 0xc0-0xdf 0 : unlock 1 : lock bit 3 cmos ram 0xe0-0xff. 0 : unlock 1 : lock bit 6-4 read as 0. bit 7 1: select upper 128-byte bank of ram 0: select lower bank logical device 7 registers (keyboard) index 0x30h 0x00, 0x00 bit 0 keyboard controller. this is a hardware setting bit by rts2j. ( note 4) 0 : disable 1 : enable bit 7-1 read as 0. index 0x70h 0x01, 0x01 bit 3-0 select irq channel used by keyboard. 0000 : none 0001 : irq1 0010 : n/a 0011 : irq3 0100 : irq4 0101 : irq5 0110 : irq6 0111 : irq7 1000 : n/a 1001 : irq9 1010 : irq10 1011 : irq11 1100 : irq12 1101 : n/a 1110 : irq14 1111 : irq15 bit 7-4 read as 0. index 0x72h 0x00, 0x00 bit 3-0 select irq channel used by ps/2 mouse. 0000 : none 0001 : irq1 0010 : n/a 0011 : irq3 0100 : irq4 0101 : irq5 0110 : irq6 0111 : irq7 1000 : n/a 1001 : irq9 1010 : irq10 1011 : irq11 1100 : irq12 1101 : n/a 1110 : irq14 1111 : irq15 bit 7-4 read as 0.
--preliminary, confidential, proprietary-- acer laboratories inc. m512x : mega i/o controller with pnp page 24 07-02-1997 document number: 512xds02.doc acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, roc tel: 886-(02) 762-8800 fax: 762-6060 index 0xf0h 0x00, 0x00 bit 0 0 : kbc clock source is 8mhz 1 : kbc clock source is 7.16mhz. bit 1 read only. indicates the type of keyboard 0 : ps2. 1 : at bit 7-2 read as 0. logical device 8 registers (common i/o) index 0x30h 0x00, 0x00 bit 0 common i/o port. 0 : disable 1 : enable bit 7-1 read as 0. index 0xe0h 0x01, n/a cio10 function definition bit 0 1 : input 0 : output bit 1 input/output signal polarity 0 : non-inverted 1 : inverted bit 2 read as 0. bit 3 0 : normal function. 1 : input function as irqin1 bit 7-4 irq mapping for irqin1. 0000 : none 0001 : irq1 0010 : n/a 0011 : irq3 0100 : irq4 0101 : irq5 0110 : irq6 0111 : irq7 1000 : n/a 1001 : irq9 1010 : irq10 1011 : irq11 1100 : irq12 1101 : n/a 1110 : irq14 1111 : irq15 index 0xe1h 0x01, n/a cio11 function definition. bit 0 0 : output 1 : input bit 1 input/output signal polarity. 0 : non-inverted 1 : inverted bit 2 read as 0. bit 3 0 : normal function. 1 : input function as irqin2 bit 7-4 irq mapping for irqin2 0000 : none 0001 : irq1 0010 : n/a 0011 : irq3 0100 : irq4 0101 : irq5 0110 : irq6 0111 : irq7 1000 : n/a 1001 : irq9 1010 : irq10 1011 : irq11 1100 : irq12 1101 : n/a 1110 : irq14 1111 : irq15 index 0xe2h 0x01, n/a cio12 func tion definition. bit 0 0 : output 1 : input bit 1 input/output signal polarity 0 : non-inverted 1 : inverted bit 2 read as 0. bit 3 0 : normal function 1 : input function as irrx2 bit 7-4 read as 0.
acer laboratories inc. --preliminary, confidential, proprietary-- m512x : mega i/o controller with pnp 07-02-1997 document number: 512xds02.doc page 25 acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, r.o.c. tel: 886-(02) 762-8800 fax: 762-6060 index 0xe3h 0x01, n/a cio13 function definition. bit 0 0 : output 1 : input bit 1 input/output signal polarity. 0 : non-inverted. 1 : inverted bit 2, 7-4 read as 0. bit 3 0 : normal function. 1 : output function as irtx2 index 0xe4h 0x01, n/a cio14 function definition. bit 0 0 : output 1 : input bit 1 input/output signal polarity 0 : non-inverted. 1 : inverted bit 2, 7-4 read as 0. bit 3 0 : normal function. 1 : select kbc p21 function index 0xe5h 0x01, n/a cio15 function definition. bit 0 0 : output. 1 : input bit 1 input/output signal polarity. 0 : non-inverted 1 : inverted bit 2, 7-4 read as 0. bit 3 0 : normal function 1 : select kbc p20 function index 0xe6h 0x01, n/a cio16 function definition. bit 0 0 : output 1 : input bit 1 input/output signal polarity. 0 : non-inverted. 1 : inverted bit 2, 7-4 read as 0. bit 3 0 : normal function 1 : output function as i 2 c clk (note2). index 0xe7h 0x01, n/a cio17 function definition. bit 0 0 : output 1 : input bit 1 input/output signal polarity. 0 : non-inverted 1 : inverted bit 2, 7-4 read as 0 bit 3 0 : normal function. 1 : select i 2 c dat function (note2). index 0xe8 0x01, n/a cio20 function definition. bit 0 0 : output 1 : input bit 1 input/output si gnal polarity. 0 : non-inverted. 1 : inverted bit 7-2 read as 0.
--preliminary, confidential, proprietary-- acer laboratories inc. m512x : mega i/o controller with pnp page 26 07-02-1997 document number: 512xds02.doc acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, roc tel: 886-(02) 762-8800 fax: 762-6060 index 0xe9h 0x01, n/a cio21 function definition. bit 0 0 : output. 1 : input bit 1 input/output signal polarity. 0 : non-inverted. 1 : inverted bit 7-2 read as 0. index 0xeah 0x01, n/a cio22 function definition. bit 0 0 : output 1 : input bit 1 input/output signal polarity. 0 : non-inverted. 1 : inverted. bit 7-2 read as 0. index 0xebh 0x01, n/a cio23 function definition. bit 0 0 : output 1 : inpu t. bit 1 input/output signal polarity. 0 : non-inverted 1 : inverted. bit 7-2 read as 0 index 0xech 0x01, n/a cio24 function definition bit 0 0 : output 1 : input bit 1 input/output signal polarity 0 : non-inverted 1 : inverted. bit 7-2 read as 0. index 0xedh 0x01, n/a cio25 function definition. bit 0 0 : output 1 : input. bit 1 input/output signal polarity. 0 : non-inverted. 1 : inverted bit 2, 7-4 read as 0. bit 3 0 : normal function. 1 : select keylock functio n index 0xeeh 0x00, n/a bit 5-0 address line[13-8] of cs0j. bit 7-6 cs0j decoding range. 00 : a[3-0]=0000b 01 : a[3-0]=00xxb 10 : a[3-0]=0xxxb 11 : a[3-0]=xxxxb index 0xefh 0x00, n/a bit 3-0 read as 0. bit 7-4 address line[7-4] of cs0j. index 0xf5h 0x01, n/a cio30 function definition. bit 0 0 : output 1 : input bit 1 input/output signal polarity. 0 : non-inverted 1 : inverted. bit 2, 7-4 read as 0. bit 3 0 : normal. 1 : input function as the new kbc clock source
acer laboratories inc. --preliminary, confidential, proprietary-- m512x : mega i/o controller with pnp 07-02-1997 document number: 512xds02.doc page 27 acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, r.o.c. tel: 886-(02) 762-8800 fax: 762-6060 index 0xf6h 0x01, n/a cio31 function definition. bit 0 0 : output 1 : input bit 1 input/output signal polarity. 0 : non-inverted. 1 : inverted bit 2, 7-4 read as 0. bit 3 0 : normal function. 1 : output function as cs0j index 0xf7h 0x01, n/a cio32 function definition. bit 0 0 : output 1 : input bit 1 input/output signal polarity. 0 : non-inverted 1 : inverted bit 2, 7-4 read as 0. bit 3 0 : normal function. 1 : output function as cs1j index 0xf8h 0x01, n/a cio33 func tion definition. bit 0 0 : output 1 : input bit 1 input/output signal polarity. 0 : non-inverted. 1 : inverted bit 7-2 read as 0. index 0xf9h 0x01, n/a cio34 function definition. bit 0 0 : output 1 : input bit 1 input/output signal polarity. 0 : non-inverted 1 : inverted bit 7-2 read as 0. index 0xfah 0x01, n/a cio35 function definition. bit 0 0 : output 1 : input bit 1 input/output signal polarity. 0 : non-inverted. 1 : inverted bit 7-2 read as 0 index 0xfbh 0x0 1, n/a cio36 function definition bit 0 0 : output 1 : input bit 1 input/output signal polarity 0 : non-inverted 1 : inverted bit 7-2 read as 0 index 0xfch 0x01, n/a cio37 function definition. bit 0 0 : output. 1 : input bit 1 input/output signal polarity 0 : non-inverted 1 : inverted bit 2, 7-4 read as 0. bit 3 0 : normal function 1 : enable the secondary kbc signal source. cio33 functions as alt_kclk cio34 functions as alt_kdat cio35 functions as alt_mclk cio36 f unctions as alt_mdat cio37 input functions as the switch control of the traditional and secondary kbc signal source. when cio37 is 1, the traditional one is selected. when 0, the secondary is selected.
--preliminary, confidential, proprietary-- acer laboratories inc. m512x : mega i/o controller with pnp page 28 07-02-1997 document number: 512xds02.doc acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, roc tel: 886-(02) 762-8800 fax: 762-6060 index 0xfdh 0x00, n/a bit 5-0 address line[13-8] of cs1j. bit 7-6 cs1j decoding range. 00 : a[3-0]=0000b 01 : a[3-0]=00xxb 10 : a[3-0]=0xxxb 11 : a[3-0]=xxxxb index 0xfeh 0x00, n/a bit 3-0 read as 0. bit 7-4 address line[7-4] of cs1j. index 0xffh 0x00, n/a bit 0 cs0j ass ertion on write cycle. 0 : disable 1 : enable bit 1 cs0j assertion on read cycle. 0 : disable 1 : enable bit 2 cs1j assertion on write cycle. 0 : disable 1 : enable bit 3 cs1j assertion on read cycle. 0 : disable 1 : enable note 1 : irq8 is reserved for use by rtc only. note 2 : the access port address of the i 2 c device is determined by cs0j. the signals on xsd[0] and xsd[1] will reflect on i 2 c_clk and i 2 c_dat individually. note 3 : during direct powerdown, access to i/o ports are denied. to wake up the device, setting 1 to corresponding bit is required. note 4 : the disable function of the device has the same behavior as direct powerdown function except the device remains at reset state. table 3-2 m512x hardware setting configuration pin name function rts1j 0 1 cfg_port 0x3f0 0x370 rts2j 0 1 kbc_en disable enable dtr1j 0 1 rtc_en disable enable dtr2j 0 1 ps2_atj (kbc) at mode ps2 mode table 3-3 drive option 1 and 2 data rate register settings (3f7) fdc 0xf4[4:3]* densel drate kb/sec drate sel 1 drate sel 0 drate opt1 drate opt0 (1) drate1 drate0 1000 1 1 0 0 1 1 1 500 0 0 0 0 1 0 0 300 0 1 0 0 0 0 1 250 1 0 0 0 0 1 0 1000 1 1 0 1 1 1 1 500 0 0 0 1 1 1 0 500 0 1 0 1 0 0 1 250 1 0 0 1 0 0 0 note : *drive table 00 = regular drives and 2.88mb 01 = 3-mode drive table 3-4 drvden output mapping for drive type table
acer laboratories inc. --preliminary, confidential, proprietary-- m512x : mega i/o controller with pnp 07-02-1997 document number: 512xds02.doc page 29 acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, r.o.c. tel: 886-(02) 762-8800 fax: 762-6060 0xf4 [1:0] drvden signal definition dt1 dt0 drvden1 drvden0 0 0 drate0 densel 1 0 drate0 drate1 0 1 drate0 ndensel 1 1 drate1 drate0 3.2 power management features the m512x contains power management features that makes it ideal for design of notebook and desktop personal computers. these features can be classified into power management of the part and the internal oscillator. the powerdown of the part is done independently of the internal oscillator in the m512x. 3.2.1 oscillator power management the m512x supports a built-in crystal oscillator that can be programmed to be either powered down or active, independent of the power state of the chip. this capability is implemented by the osc-off bit in the 0x22. when osc- off is set high, the internal oscillator is off. when the external oscillator is used, power can be saved by turning off the internal oscillator. if the internal oscillator is used, the oscillator may be powered up (even when the rest of the chip is powered off) allowing the chip to wake up quickly and be in a stable state. it is recommended to keep the internal oscillator on even at the powerdown state. the main reason for this is that the recovery time of the oscillator during wake-up may take tens of milli-seconds under the worst case, which may create problems with any sensitive application software. in a typical application, the internal oscillator should be on unless the system goes into a power saving or standby mode. such a mode request would be made by a system time-out or by a user. in this case, the system software would take over and must turn on the oscillator sufficiently ahead of awakening the part. in the case of the external oscillators, the power-up characteristics are similar. if the external source remains active during the time the m512x is powered down, then the recovery time effect is minimized. 3.2.2 part power management this section deals with the power management of the rest of the chip excluding the oscillator. this part shows how powerdown modes and wake up modes are activated. 3.2.2.1 powerdown modes of fdc the rest of the chip is powered down in two ways: direct powerdown and automatic powerdown. direct powerdown results in immediate shutdown of the part without regard to the current state of the part. automatic powerdown results when certain conditions become true within the part. a. direct powerdown direct powerdown is conducted via the powerdown bit in the dsr register (bit 6) or fdc_pwd bit in 0x22. programming this bit high will powerdown m512x after the part is internally reset. all current status is lost if this type of powerdown mode is used. the part can exit powerdown from this mode via any hardware or software reset. this type of powerdown will override the automatic powerdown. if the part is in automatic powerdown when the dsr powerdown is issued, then all the previous status of the part will be lost, and the m512x will be reset to its default values. b. auto powerdown automatic powerdown is conducted via a "set powerdown mode" command. there are four conditions required before the part will enter powerdown. all these conditions must be true for the part to initiate the powerdown sequence. these conditions are listed as follows: 1. the motor enable pins me[0:3] must be inactive, 2. the part must be idle; this is indicated by msr = 80h and int = 0 (int may be high even if msr = 80h due to polling interrupt), 3. the head unload timer must have expired, and 4. the auto powerdown timer must have timed out. the command can be used to enable powerdown by setting the autopd bit in the command to high. the command also provides a capability of programming a minimum power-up time via the min dly bit in the command. the minimum power-up time refers to a minimum amount of time the part will remain powered-up after being awakened or reset. an internal timer is initiated as soon as the auto powerdown command is enabled. the part is then powered down provided all the remaining conditions are met. any software reset will reinitialize the timer. changing of data rate extends the auto powerdown timer by up to 10 ms, but only if the data rate is changed during the countdown. disabling the auto powerdown mode cancels the timers and holds the m512x out of auto powerdown.
--preliminary, confidential, proprietary-- acer laboratories inc. m512x : mega i/o controller with pnp page 30 07-02-1997 document number: 512xds02.doc acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, roc tel: 886-(02) 762-8800 fax: 762-6060 3.2.2.2 powerdown mode of uart and printer uart1, uart2 and printer can enter direct powerdown or auto powerdown respectively by setting their relative powerdown bit in the 0x22 and 0x23. 3.2.2.3 wake up modes of fdc this section describes the conditions for awakening the part from both direct and automatic powerdown. power conservation of battery life is the main reason power management is required. this means that the m512x must be kept in powerdown state as long as possible and should be powered up as late as possible without compromising software transparency. to keep the part in powerdown mode as late as possible implies that the part should wake-up as fast as possible. however, some amount of time is required for the part to exit powerdown state and prepare the internal microcontroller to accept commands. application software is very sensitive to such a delay and in order to maintain software transparency, the recovery time of the wake-up process must be carefully controlled by the system software. a. wake up from dsr powerdown if the m512x enters powerdown through the dsr powerdown bit, it must be reset to exit. any form of software or hardware reset will serve, although dsr is recommended. no other register access will wake up the part, including writing to the dor's motor enable (me[0:3]) bits. if dsr powerdown is used when the part is in auto powerdown, the dsr powerdown will override the auto powerdown. however, when the part is awakened by a software reset, the auto powerdown command (including the minimum delay timer) will again become effective as previously programmed. if the part is awakened via a hardware reset, the auto powerdown is disabled. after reset, the part will go through a normal sequence. the drive status will be initialized. the fifo mode will be set to default mode on a hardware reset or on a software reset if the lock command is not blocking it. finally, after a delay, the polling interrupt will be issued. b. wake up from auto powerdown if the part enters the powerdown state through the auto powerdown mode, then the part can be awakened by reset or by appropriate access to certain registers. if a hardware or software reset is used, then the part goes through the normal reset sequence. if the access is through the selected registers, then the m512x resumes operation as though it was never in powerdown. besides activating the reset pin or one of the software reset bits in the dor or dsr, the following register accesses will wake-up the part: 1. enabling any one of the motor enable bits in the dor register (reading the dor does not wake-up the part) 2. a read from the msr register 3. a read or write to the fifo register any of these actions will wake-up the part. once awake, m512x will initiate the auto powerdown time for 10 ms or 0.5 sec. (depending on the min dly bit the auto powerdown command). the part will powerdown again when all the powerdown conditions stated in the auto powerdown section are satisfied.
acer laboratories inc. --preliminary, confidential, proprietary-- m512x : mega i/o controller with pnp 07-02-1997 document number: 512xds02.doc page 31 acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, r.o.c. tel: 886-(02) 762-8800 fax: 762-6060 section 4 : floppy disk controller 4.1 register overview the integrated fdc of the m512x part is register- and hardware-level compatible with the industry standard 765a and 82077sl standards. table 4-1 lists the i/o address map of the fdc controller. table 4-2 is the summary of fdc register hardware reset. table 4-1 fdc controller i/o address map a2 a1 a0 r/w register 0 0 0 r sra (ps/2 mode only) 0 0 1 r srb (ps/2 m ode only) 0 1 0 r/w digital output register dor 0 1 1 r/w tape drive register tdr 1 0 0 r main status register msr 1 0 0 w data rate select register dsr 1 0 1 r/w data (first in first out) fifo 1 1 0 - reserved 1 1 1 r digital input register dir 1 1 1 w configuration control register ccr * when this location is accessed, only bit 7 is driving, all other bits are held tristate. table 4-2 summary of fdc register hardware reset and powerdown state register bits state 7 6 5 4 3 2 1 0 i/o address map dor(r/w) h/w reset state 0 0 0 0 0 0 0 0 3f2 tdr(r/w) h/w reset state _ _ _ _ _ _ 0 0 3f3 msr(r) h/w reset state 0 x x x x x x x 3f4 dsr(w) h/w reset state 0 0 0 0 0 0 1 0 3f4 dir(r) h/w reset state na _ _ _ _ _ _ _ 3f7 ccr(w) h/w reset state _ _ _ _ _ _ 1 0 3f7 sra(r) h/w reset state 0 na 0 na 0 na na 0 3f0 srb(r) h/w reset state 1 1 0 0 0 0 0 0 3f1
--preliminary, confidential, proprietary-- acer laboratories inc. m512x : mega i/o controller with pnp page 32 07-02-1997 document number: 512xds02.doc acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, roc tel: 886-(02) 762-8800 fax: 762-6060 4.2 register description this section describes the register bits for all the registers that are directly accessible to the cpu. 4.2.1 status register a (sra) address 3f0 read only this register is read-only and monitors the state of the irq6 pin and several disk interface pins in ps/2 modes. the sra can be accessed any time when it is in ps/2 mode. in at mode, the data bus pins d0-d7 are held in a high impedance state for a read of address 3f0h. ps/2 mode bit name 7 int pending 6 drv2j 5 step 4 trk0j 3 hdsel 2 indxj 1 wpj 0 dir bit 7 interrupt pending : the state of the floppy disk interrupt output (active high). bit 6 drv2j : drv2 disk interface input pin, indicates that a second drive has been installed. bit 5 step : step output disk interface output pin (active high) bit 4 track 0 : trk0 disk interface input (active low) bit 3 head select : hdsel disk interface input. a logic "1" selects side 1 and a logic "0" selects side 0. bit 2 index : index disk interface input (active low) bit 1 write protect : write protect disk interface input. a logic "0" indicates that the disk is write protected. bit 0 direction : head movement direction (active high). a logic "1" indicates inward direction a logic "0" outward. 4.2.2 status register b (srb) address 3f1 read only this register is read-only and monitors the state of several disk interface pins, in ps/2 modes. the srb can be accessed at any time during ps/2 mode. in at mode, the data bus pins d0-d7 are held in a high impedance state for a read of address 3f1h. ps/2 mode bit name 7 1 6 1 5 drive sel0 4 wdata toggle 3 rdata toggle 2 wgate 1 moten1 0 moten0 bit 7 reserved : always read as a logic "1" bit 6 reserved : always read as a logic "1" bit 5 drive select 0 : reflects the status of the drive select bit 0 of dor (address 3f2 bit 0). this bit is cleared after a hardware reset, it is unaffected by a software reset bit 4 write data toggle : this bit changes bit 3 read data toggle : every inactive edge of the rdata input causes this bit to c hange state. state at every inactive edge of the wdata bit 2 write gate : the wgate disk interface output (active high) bit 1 motor enable 1 : the mtr1 disk interface output pin. this bit is low after a hardware reset and unaffected by a software reset. bit 0 motor enable 0 : the mtr0 disk interface output pin. this bit is low after a hardware reset and unaffected by a software reset.
acer laboratories inc. --preliminary, confidential, proprietary-- m512x : mega i/o controller with pnp 07-02-1997 document number: 512xds02.doc page 33 acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, r.o.c. tel: 886-(02) 762-8800 fax: 762-6060 4.2.3 digital output register (r/w) address 3f2 r/w table 4-3 digital output register description bit description d7 motor enable 3: this controls the motor for drive 3, mtr3. the output is high when it is inactive, and low when it is active. this bit and dor bit 6 provide information that control the mtr1 and 0 pins, respectively when bit 7 of the configuration register is set. d6 motor enable 2: same function as d7 except for drive 2's motor. note that this signal is not brought out to a pin. d5 motor enable 1: this bit controls the motor for drive 1's motor. when this bit is 0, the mtr1 output is high. d4 motor enable 0: same as d5 except for drive 0's motor. d3 dma enable: when set to a 1, this enables the drq, dak, and int pins. a zero disables these signals. d2 reset controller: this bit resets the controller when 0 and enables normal operation when it is a 1. it does not affect the drive control or data rate registers which are reset only by a hardware reset. d1~d0 drive select: these two pins are encoded for the four drive select, and are gated with the motor enable lines, so that only one drive is selected when its motor enable is active. table 4-4 internal 4 drive decode - normal digital output register drive select outputs motor on outputs d7 d6 d5 d4 d1 d0 ds1j ds0j mtr1j mtr0j x x x 1 0 0 1 0 /d5 /d4 x x 1 x 0 1 0 1 /d5 /d4 x 1 x x 1 0 1 1 /d5 /d4 1 x x x 1 1 1 1 /d5 /d4 0 0 0 0 x x 1 1 /d5 /d4 table 4-5 internal 4 drive decode - drives 0 and 1 swapped digital output register drive select outputs motor on outputs d7 d6 d5 d4 d1 d0 ds1j ds0j mtr1j mtr0j x x x 1 0 0 0 1 /d4 /d5 x x 1 x 0 1 1 0 /d4 /d5 x 1 x x 1 0 1 1 /d4 /d5 1 x x x 1 1 1 1 /d4 /d5 0 0 0 0 x x 1 1 /d4 /d5
--preliminary, confidential, proprietary-- acer laboratories inc. m512x : mega i/o controller with pnp page 34 07-02-1997 document number: 512xds02.doc acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, roc tel: 886-(02) 762-8800 fax: 762-6060 4.2.4 tape drive register (tdr) address 3f3 r/w this register is included for 82077 software compatibility. the robust data separator used in the m512x does not require its characteristics modified for tape support. the contents of this register are not used internally to the device. the tdr is unaffected by a software reset. bits 2-7 are tri-stated when read in this mode. normal floppy mode normal mode. register 3f3h contains only bits 0 and 1. when this register is read, bits 2- 7 are at high impedance. db7 db6 db5 db4 db3 db2 db1 db0 reg 3f3 tri-state tri- state tri-state tri-state tri-state tri- state tapesel1 tapesel0 enhanced floppy mode 2 (os2) register 3f3 for enhanced floppy mode 2 operation db7 db6 db5 db4 db3 db2 db1 db0 reg 3f3 media id1 media id0 drive type id floppy boot drive tapesel1 tapesel0 for this mode, drate0 and drate1 pins are inputs and these inputs are gated into bits 6 and 7 of the 3f3 register. these two bits are not affected by any reset. bit 7 media id 1 read only (pin 19) see table next page bit 6 media id 0 read only (pin 20) see table next page bits 5 and 4 drive type id - these bits reflect two of fdc 0xf2 configuration register bits. (please see next page). bits 3 and 2 floppy boot drive . these bits show the value of fdc 0xf1 configuration register bits. bits 1 and 0 - tape drive select (r/w). same as in normal and enhanced floppy mode 1.
acer laboratories inc. --preliminary, confidential, proprietary-- m512x : mega i/o controller with pnp 07-02-1997 document number: 512xds02.doc page 35 acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, r.o.c. tel: 886-(02) 762-8800 fax: 762-6060 media id1 media id0 drate1 media id1 drate0 media id0 pin 19 fdc 0xf1-db5=0 fdc 0xf1--db5=1 pin 20 fdc 0xf1-db4=0 fdc 0xf1-db4=1 0 0 1 0 0 1 1 1 0 1 1 0 drive type id digital output register register 3f3 - drive type id bit 1 bit 0 bit 5 bit 4 0 0 fdc 0xf2 - bit 1 fdc 0xf2 - bit 0 0 1 fdc 0xf2 - bit 3 fdc 0xf2 - bit 2 1 0 fdc 0xf2 - bit 5 fdc 0xf2 - bit 4 1 1 fdc 0xf2 - bit 7 fdc 0xf2 - bit 6 4.2.5 main status register address 3f4h read only the read-only main status register indicates the current status of the disk controller. it is always available to be read. one of its functions is to control the flow of data to and from the data register. it also indicates when the disk controller is ready to send or receive data. it should be read before each byte is transferred to or from the data register except during a dma transfer. no delay is required when reading this register after a data transfer. table 4-8 main status register description bit description d7 request for master: indicates that the data register is ready to send or receive data from the cpu. this bit is cleared immediately after a byte transfer, and is set again as soon as the m512x is ready for the next byte. d6 data direction: indicates whether the controller is expecting a byte to be written to (0) or read from (1) the data register. d5 non-dma execution: bit is set only during the execution phase of a command if it is in the non-dma mode. in other words, if this bit is set, the multiple byte data transfer (in the execution phase) must be monitored by the cpu either through interrupts, or software polling as described in the processor software interface section. d4 command in progress: bit is set after the first byte of the command phase is written. bit is cleared after the last byte of the result phase is read. if there is no result phase in a command, the bit is cleared after the last byte of the command phase is written. d3~d0 drives 3~0 seeking: set after the last byte of the command phase of a seek or recalibrate command is issued for drives 3~0, respectively. cleared after reading the first byte in the result phase of the sense interrupt command for this drive.
--preliminary, confidential, proprietary-- acer laboratories inc. m512x : mega i/o controller with pnp page 36 07-02-1997 document number: 512xds02.doc acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, roc tel: 886-(02) 762-8800 fax: 762-6060 4.2.6 data rate select register (dsr) address 3f4 write only table 4-9 datarate select register description bit description d7 s/w reset behaves the same as dor reset except that this reset is self clearing. d6 powerdown bit implements direct powerdown. setting this bit high puts the fdc into the powerdown state regardless of the state of the part. the part is reset internally and then goes into powerdown. no status is saved and any operation in progress is aborted. this powerdown mode does not turn off the internal oscillator. any hardware or software reset will exit the m512x from this powerdown state. d5 reserved d4~d2 precomp 0-2 adjusts the wrdata output to the and disk to compensate for magnetic media phenomena known as bit shifting. the data patterns that are susceptible to bit shifting are well understood and the m512x offsets the data pattern as it is written to the disk. the amount of precompensation depends upon the drive and media but in most cases the default value is acceptable. the m512x starts precompensating the data pattern starting on track 0. the configure command can change the starting track for precompensation. table 4-10 lists the precompensation values that can be selected and table 4-11 lists the default precompensation values. the default value is selected if the three bits are zeros. d1~d0 drate 0-1 select one of the four data rates as listed in table 4-12. the default value is 250 kbps upon a chip ("hardware") reset. other ("software") resets do not affect the drate or precomp bits. table 4-10 precompensation delay values precomp 432 bits precompensation delay -- disabled 111 0.00ns 001 41.67ns 010 83.34ns 011 125.00ns 100 166.67ns 101 208.33ns 110 250.00ns 000 default
acer laboratories inc. --preliminary, confidential, proprietary-- m512x : mega i/o controller with pnp 07-02-1997 document number: 512xds02.doc page 37 acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, r.o.c. tel: 886-(02) 762-8800 fax: 762-6060 table 4-11 defau lt precompensation delay values table 4-12 data rates data rate precompensation delay dratesel data rate 1 mbps 41.67ns mfm fm 500 kbps 125ns 1 1 1 mbps illegal 300 kbps 125ns 0 0 500 kbps 250 kbps 250 kbps 125ns 0 1 300 kbps 150 kbps 1 0 250 kbps 125 kbps 4.2.7 data register (r/w) address 3f5 r/w this is the location through which all commands, data, and status flow between the cpu and the fdc. during the command phase, the cpu loads the controller's commands into this register based on the status register request for master and data direction bits. the result phase transfers the status registers and header information to the cpu in the same fashion. all command parameter information and disk data transfers go through the fifo. the 16-byte fifo has programmable threshold values. data transfers are generated by the rqm and dio bits in the main status register. the fifo defaults to an m5105 compatible mode after a "hardware" reset (reset via pin 1). "software" resets (reset via dor or dsr register) can also place the m512x into m5105-a3/a4-compatible mode if the lock bit is set to "0" this maintains pc-at hardware compatibility. the default values can be changed through the configure command (enable full fifo operation with threshold control). the advantage of the fifo is that it allows the system a larger dma latency without causing disk error. table 4-13 gives several examples of the delays with a fifo. the data is based upon the following formula: threshold # * 1/data rate * 8 - 1.5 us = delay table 4-13 fifo service delay fifo threshold maximum delay to servicing examples at 1 mbps data rate 1 byte 1 * 8 us - 1.5 us = 6.5 us 2 bytes 2 * 8 us - 1.5 us = 14.5 us 8 bytes 8 * 8 us - 1.5 us = 62.5 us 15 bytes 15 * 8 us - 1.5 us = 118.5 us fifo threshold maximum delay to servicing examples at 500 mbps data rate 1 byte 1 * 16 us - 1.5 us = 14.5 us 2 bytes 2 * 16 us - 1.5 us = 30.5 us 8 bytes 8 * 16 us - 1.5 us = 126.5 us 15 bytes 15 * 16 us - 1.5 us = 238.5 us
--preliminary, confidential, proprietary-- acer laboratories inc. m512x : mega i/o controller with pnp page 38 07-02-1997 document number: 512xds02.doc acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, roc tel: 886-(02) 762-8800 fax: 762-6060 at the start of a command, the fifo action is always disabled and command parameters must be sent based upon the rqm and dio bit settings. as the m512x enters the command execution phase, it clears the fifo of any data to ensure that invalid data is not transferred. an overrun or underrun will terminate the current command and the transfer of data. disk writes will complete the current sector by generating a 00 pattern and valid crc. 4.2.8 configuration control register (ccr, pc-at modes) address 3f7 write only table 4-14 configuration control register description bit description d7~d2 not used. d1, d0 data rate select: these bits set the data- rate and write-precompensation values for the disk controller. after a hardware reset, these bits are set to 1, 0 (250 kbps). (please refer to table 4-12) 4.2.9 digital input register (dir, read) address 3f7 read only table 4-15 digital input register description (pc/at mode) bit description d7 dskchg monitors the pin of the same name and reflects the opposite value seen on the disk cable, regardless of the value of /invert/. the dskchg bit is forced inactive along with all the inputs from the floppy disk drive. all the other bits remain tri-stated. d6~d0 these bits are reserved for use by the hard disk controller, thus during a read of this register, these bits are in high impedance state. table 4-15b digital input register (ps/2 mode) bit description d7 dskchg monitors the pin of the same name and reflects the opposite value seen on the disk cable. d6~d3 undefined, always read as logic "1". d2~d1 data rate select. these bits control the data rate of the floppy controller. these bits are unaffected by a software reset, and are set to 250 kbps after a hardware reset. d0 high density. this bit is low whenever the 500 kbps or 1 mbps data rates are selected, and high when 250 kbps and 300 kbps are selected.
acer laboratories inc. --preliminary, confidential, proprietary-- m512x : mega i/o controller with pnp 07-02-1997 document number: 512xds02.doc page 39 acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, r.o.c. tel: 886-(02) 762-8800 fax: 762-6060 4.3 result phase status registers the result phase of a command contains bytes that hold status information. the format of these bytes are described in the following sections. do not confuse these register bytes with the main status register which is a read-only register that is always available. the result phase status registers are read from the data register only during the result phase. 4.3.1 status register 0 (st0) table 4-16 status register 0 description bit description d7~d6 interrupt code : 00 = normal termination of command. 01 = abnormal termination of command. command was executed, but not successfully completed. 10 = invalid co mmand issue. command issued was not recognized as a valid command. 11 = ready changed state during the polling mode. d5 seek end: this bit is set after a seek or recalibrate command is completed by the controller. used during sense interrupt command. d4 equipment check: this bit is set after a recalibrate command track 0 signal failed to occur. used during sense interrupt command. d3 not used: 0 d2 head number: at end of execution phase. d1, d0 drive select: at end of execution phase. 00 = drive 0 selected 01 = drive 1 selected 10 = drive 2 selected 11 = drive 3 selected 4.3.2 status register 1 (st1) table 4-17 status register 1 description bit description d7 end of track: this bit is set when the controller has transferred the last byte of the last sector without the tc pin becoming active. the last sector is the end-of-track sector number programmed in the command phase. d6, d3 not used: 0 d5 crc error: if this bit is set and bit 5 of st2 is clear, then there was a crc error in the address field of the correct sector. if bit 5 of st2 is set, then there was a crc error in the data field. d4 over run: this bit is set when the controller was not serviced by the cpu soon enough during a data transfer in the execution phase. table 4-18 shows the time values. d2 no data: this bit is set for any three possible problems: 1. controller cannot find the sector specified in the command phase during the execution of a read, write, or scan command. an address mark was found even if it is not a blank disk. 2. controller cannot read any address fields without a crc error during read id command. 3. controller cannot find the starting sector during execution of read a track command. d1 not writable: set if the write protect pin is active when a write or format command is issued. d0 missing address mark: if this bit is set and bit 0 of st2 is clear then the disk controller cannot detect any address field address mark after two disk revolutions. if bit 0 of st2 is set, then the disk controller cannot detect the data field address mark.
--preliminary, confidential, proprietary-- acer laboratories inc. m512x : mega i/o controller with pnp page 40 07-02-1997 document number: 512xds02.doc acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, roc tel: 886-(02) 762-8800 fax: 762-6060 table 4-18 maximum time allowed to service an interrupt or acknowledge a dma request in execution phase data rate time to service 125 62.0 us 250 30.0 us 500 14.0 us 125 6.0 us 4.3.3 status register 2 (st2) table 4-19 status register 2 description bit description d7 not used: 0 d6 control mark: this bit is set if the controller tries to read a sector which contained a deleted data address mark during execution of read-data or scan commands. or, if a read-deleted-data command was executed, a regular address mark is detected. d5 crc error in data field: this bit is set if the controller detects a crc error in the data field. bit 5 of st1 is also set. d4 wrong track: this bit is only set if the desired sector is not found, and the track number recorded on any sector of the current track is different from that stored in the track register. d3 scan equal hit: this bit is only set if the equal condition is satisfied during any scan command. d2 scan not satisfied: this bit is set if the controller cannot find a sector on the track number recorded on any sector on the track which meets the desired condition during scan commands. d1 bad track: this bit is only set if the desired sector is not found, and the track number recorded on any sector on the track is different from that stored in the track register and the recorded track number is ff. d0 missing address mark in data field: this bit is set if the controller cannot find the data field address mark during read/scan command. bit 0 of st1 is also set.
acer laboratories inc. --preliminary, confidential, proprietary-- m512x : mega i/o controller with pnp 07-02-1997 document number: 512xds02.doc page 41 acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, r.o.c. tel: 886-(02) 762-8800 fax: 762-6060 4.3.4 status register 3 (st3) table 4-20 status register 3 description bit description d7 not used: 0 d6 write protect status: this bit is the complement of the associated fdc interface pin for the drive selected in dcr. d5 not used: 1 d4 track 0 status: this bit is the complement of the associated fdc interface pin for the drive selected in the dcr. d3 not used: 0 d2 head select status: this bit shows the status of the associated bit in the sense-drive-status command phase. d1, d0 drive selected: these bits show the status of the associated bits in the sense-drive-status command phase. these bits show the same status as st0 bits 1, 0. 00 = drive 0 selected 01 = drive 1 selected 10 = drive 2 selected 11 = drive 3 selected
--preliminary, confidential, proprietary-- acer laboratories inc. m512x : mega i/o controller with pnp page 42 07-02-1997 document number: 512xds02.doc acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, roc tel: 886-(02) 762-8800 fax: 762-6060 4.4 controller functional description 4.4.1 controller phases the fdc handles commands in three phases ? command, execution and result. each phase is described below. 4.4.1.1 command phase the cpu writes a series of bytes to the data register. these bytes indicate the command desired and the particular parameters required for the command. all the bytes must be written in the order specified in the command description table. the execution phase starts immediately after the last byte in the command phase is written. the main status register controls the flow of command bytes, and must be polled by the software before writing each command phase byte to the data register. prior to writing a command byte, the bit 7 must be set and bit 6 must be cleared in the msr. after the first command byte is written to the data register, the bit 4 in msr is also set and remain set until the last result phase byte is read. if there is no result phase, it is cleared after the last command byte is written. a new command may be initiated after reading all the result bytes from the previous command. 4.4.1.2 execution phase the disk controller performs the desired command. some commands require the cpu to read or write data to or from the data register during this phase. some commands such as seek control the read/write head movement on the disk drive. some commands does not involve any action by the up or disk drive, and consists of an internal operation by the controller. if there is data to be transferred between the up and the controller, there are three methods that can be used, dma mode, interrupt mode, and software polling mode. all of these data transfer modes work with the fifo enabled or disabled. 4.4.1.2.1 dma mode if the dma mode is selected, a dma request is generated in the execution phase when each byte is ready to be transferred. to enable dma operations during the execution phase, the dma mode bit in the specify command must be enabled, and the dma signals must be enabled in the drive control register. the dma controller responds to the dma request with a dma-acknowledge and a read- or write- strobe. the dma request is cleared by the active edge of the dma-acknowledge. after the last byte is transferred, an interrupt is generated, indicating the beginning of the result phase. tc is asserted to terminate an operation. due to internal gating, tc is only recognized when the -dak input is low. 4.4.1.2.2 interrupt mode if the non-dma mode is selected, an interrupt is generated in the execution phase when each byte is ready to be transferred. the main status register should be read to verify that the interrupt is for a data transfer. bits 5 and 7 of the main status register is set. the interrupt is cleared when the byte is transferred to or from the data register. the cpu should transfer the byte within the allotted time. if the byte is not transferred within the time allotted, an overrun error is indicated in the result phase when the command terminates at the end of the current sector. an interrupt is also generated after the last byte is transferred. this indicates the beginning of the result phase. 4.4.1.2.3 software polling if the non-dma mode is selected and interrupts are not suitable, the cpu can poll the main status register during the execution phase to determine when a byte is ready to be transferred. the bit 7 of the main status register reflects the state of the interrupt pin. otherwise, the data transfer is similar to the interrupt mode described above. 4.4.1.3 result phase during the result phase, the up reads a series of bytes from the data register. these bytes indicate the status of the command. this status may indicate whether the command executed properly, or contain some control information. the bit 7 and bit 6 in the msr must both be set before each result byte can be read. after the last result byte is read, the bit 4 in the msr is cleared, and the controller is ready for the next command.
acer laboratories inc. --preliminary, confidential, proprietary-- m512x : mega i/o controller with pnp 07-02-1997 document number: 512xds02.doc page 43 acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, r.o.c. tel: 886-(02) 762-8800 fax: 762-6060 table 4-21 m512x fdc command set read data command phase mt mfm sk 0 0 1 1 0 ips 0 0 0 0 hd dr1 dr0 track number drive head number sector number bytes per sector end of track sector number intersector gap number data length execution phase : data read from disk drive is transferred to system via dma or non-dma modes. result phase status register 0 status register 1 status register 2 track number head number sector number bytes per sector read deleted data command phase mt mfm sk 0 1 1 0 0 ips 0 0 0 0 hd dr1 dr0 track number drive head number sector number bytes per sector end of track sector number intersector gap number data length execution phase : data read from disk drive is transferred to system via dma or non-dma modes. result phase status register 0 status register 1 status register 2 track number head number sector number bytes per sector read a track command phase 0 mfm 0 0 0 0 1 0 ips 0 0 0 0 hd dr1 dr0 track number drive head number sector number bytes per sector end of track sector number intersector gap number data length execution phase : data read from disk drive is transferred to system via dma or non-dma modes. result phase status register 0 status register 1 status register 2 track number head number sector number bytes per sector read id command phase 0 mfm 0 0 1 0 1 0 0 0 0 0 0 hd dr1 dr0 execution phase : controller reads first id field header bytes it can find and reports these bytes to the system in the result bytes result phase status register 0 status register 1 status register 2 track number head number sector number bytes per sector
--preliminary, confidential, proprietary-- acer laboratories inc. m512x : mega i/o controller with pnp page 44 07-02-1997 document number: 512xds02.doc acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, roc tel: 886-(02) 762-8800 fax: 762-6060 write data command phase mt mfm 0 0 0 1 0 1 ips 0 0 0 0 hd dr1 dr0 track number drive head number sector number bytes per sector end of track sector number intersector gap number data length execution phase : data is transferred from the system to the controller via dma or non-dma modes and written to the disk. result phase status register 0 status register 1 status register 2 track number head number sector number bytes per sector write deleted data command phase mt mfm 0 0 1 0 0 1 ips 0 0 0 0 hd dr1 dr0 track number drive head number sector number bytes per sector end of track sector number intersector gap number data length execution phase : data is transferred from the system to the controller via dma or non-dma modes and written to the disk. result phase status register 0 status register 1 status register 2 track number head number sector number bytes per sector format a track command phase 0 mfm 0 0 1 1 0 1 0 0 0 0 0 hd dr1 dr0 bytes per sector sector per track format gap data pattern execution phase : system transfers four id bytes per sector to the floppy controller via dma or non-dma modes. the entire track is formatted. the data block in the data field of each sector is filled with the data pattern byte result phase status register 0 status register 1 status register 2 undefined undefined undefined undefined scan equal command phase mt mfm sk 1 0 0 0 1 ips 0 0 0 0 hd dr1 dr0 track number drive head number sector number bytes per sector end of track sector number intersector gap number data length execution phase : data transfer from system to controller is compared to data read from disk result phase status register 0 status register 1 status register 2 track number head number sector number bytes per sector
acer laboratories inc. --preliminary, confidential, proprietary-- m512x : mega i/o controller with pnp 07-02-1997 document number: 512xds02.doc page 45 acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, r.o.c. tel: 886-(02) 762-8800 fax: 762-6060 scan high or equal command phase mt mfm sk 1 1 1 0 1 ips 0 0 0 0 hd dr1 dr0 track number drive head number sector number bytes per sector end of track sector number intersector gap number data length execution phase : data transfer from system to controller is compared to data read from disk result phase status register 0 status register 1 status register 2 track number head number sector number bytes per sector scan low or equal command phase mt mfm sk 1 0 0 0 1 ips 0 0 0 0 hd dr1 dr0 track number drive head number sector number bytes per sector end of track sector number intersector gap number data length execution phase : data transfer from system to controller is compared to data read from disk result phase status register 0 status register 1 status register 2 track number head number sector number bytes per sector verify command phase mt mfm sk 1 0 1 1 0 0 0 0 0 0 hd dr1 dr0 track number drive head number sector number bytes per sector end of track sector number intersector gap number data length execution phase : data is read from disk but not transferred to the system. result phase status register 0 status register 1 status register 2 track number head number sector number bytes per sector dumpreg command phase 0 0 0 0 1 1 1 0 execution phase : internal registers read result phase present track number on drive 0 present track number on drive 1 present track number on drive 2 present track number on drive 3 step rate time motor off time motor on time dma sector per track/end of track lock 0 d3 d2 d1 d0 gap wg 0 eis fifo poll fifothr pretrk perpendicular mode command phase 0 0 0 1 0 0 1 0 ow 0 d3 d2 d1 d0 gap wg execution phase : internal registers are written. no result phase .
--preliminary, confidential, proprietary-- acer laboratories inc. m512x : mega i/o controller with pnp page 46 07-02-1997 document number: 512xds02.doc acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, roc tel: 886-(02) 762-8800 fax: 762-6060 configure command phase 0 0 0 1 0 0 1 1 0 0 0 0 0 0 0 0 0 eis fifo poll fifothr pretrk execution phase: internal registers are written. no result phase recalibrate command phase 0 0 0 0 0 1 1 1 0 0 0 0 0 0 dr1 dr0 execution phase: disk drive head is stepped out to track 0. no result phase relative seek command phase 1 dir 0 0 1 1 1 1 0 0 0 0 0 hd dr1 dr0 relative track number execution phase: disk drive head stepped in or out a programmable number of tracks. no result phase seek command phase 0 0 0 0 1 1 1 1 0 0 0 0 0 hd dr1 dr0 new track number execution phase: disk drive head is stepped in or out to a desired track. no result phase sense drive status command phase 0 0 0 0 0 1 0 0 0 0 0 0 0 hd dr1 dr0 execution phase: disk drive status information is detected and reported. result phase status register 3 sense interrupt command phase 0 0 0 0 1 0 0 0 execution phase: status of interrupt is reported result phase status register 0 present track number specify command phase 0 0 0 0 0 0 1 1 step rate time motor off time motor on time dma execution phase: internal registers are written. no result phase powerdown mode command phase 0 0 0 1 0 1 1 1 0 0 0 0 0 0 dly apd execution phase: internal registers are written result phase 0 0 0 0 0 0 dly apd version command phase 0 0 0 1 0 0 0 0 result phase 1 0 0 1 0 0 0 0 lock command phase lock 0 0 1 0 1 0 0 execution phase : internal registers are written. result phase 0 0 0 lock 0 0 0 0 invalid command phase invalid codes result phase status register 0 (80h)
acer laboratories inc. --preliminary, confidential, proprietary-- m512x : mega i/o controller with pnp 07-02-1997 document number: 512xds02.doc page 47 acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, r.o.c. tel: 886-(02) 762-8800 fax: 762-6060 4.6 command description 4.6.1 read data the read data op-code is written to the data register followed by 8 bytes as specified in the command description table. after the last byte is written, the controller starts looking for the correct sector header. once the controller is found, the controller sends data to the cpu. after one sector is finished, the sector number is incremented by one and this new sector is searched for. if mt (multi-track) is set, both sides of one track can be read. starting on side zero, the sectors are read until the sector number specified by end of track sector number is reached. then, side one is read by starting with sector number one. in dma mode, the read-data command continues to read until the tc pin is set. this means that the dma controller should be programmed to transfer the correct number of bytes. tc should be controlled by the cpu and be asserted when enough bytes are received. an alternative to these methods of stopping the read-data command is to program the end of track sector number as the last sector number that to be read. the controller stops reading the disk with an error message indicating that it tried to access a sector number beyond the end of the track. the number of data bytes per sector parameter is defined in table 4-27. if this is set to zero, the data length parameter defines the number of bytes that the controller transfers to the cpu. if the data length specified is smaller than 128, the controller still reads the entire 128 byte sector and checks the crc, though only the number of bytes specified by the data length parameter are transferred to the cpu. data length parameter should not be set to zero. if the number of bytes per sector parameter is not zero, the data length parameter has no meaning and should be set to ffh. table 4-27 sector size selection bytes/sector number of bytes code in data field 0 128 1 256 2 512 3 1024 4 2048 5 4096 6 8192 if the implied seek mode is enabled by both the mode command and the ips bit in this command, a seek is performed to the track number specified in the command phase. the controller also waits for the head-settle-time if the implied seek is enabled. after all these conditions are met, the controller searches for the specified sector by comparing the track number, head number, sector number, and number of bytes/sector given in the command phase with the appropriate bytes read off the disk in the address fields. if the correct sector is found, but there is a crc error in the address field, bit 5 of st1 (crc error) is set and an abnormal termination is indicated. if the correct sector is not found, bit 2 of st1 (no data) is set and an abnormal termination is indicated. in addition to this, if any address field track number is ff, bit 1 of st2 (bad track) is set or, if any address field track number is different from that specified in the command phase, bit 4 of st2 (wrong track) is set. after finding the correct sector, the controller reads that data field. if a deleted data mark is found and the sk bit is set, the sector is not read, bit 6 of st2 (control mark) is set, and the next sector is searched for. if a deleted data mark is found and the sk bit is not set, the sector is read, bit 6 of st2 (control mark) is set, and the read terminates with a normal termination. if a crc error is detected in the data field, bit 5 is set to both st1 and st2 (crc error) and an abnormal termination is indicated. if no problems occur in the read command, the read continues from one sector to the next in logical order (not physical order) until either tc is set or an error occurs. if a disk has not been inserted into the disk drive, there are many opportunities for the controller to hang. it does this if it is waiting for a certain number of disk revolutions. if this occurs, the controller can be forced to abort the command by writing a byte to the data register. an interrupt is generated when an execution phase of the read data command terminates. table 4-28 shows the values that are read back in the result phase. if an error occurs, the result bytes indicate the sector being read when the error occurred.
--preliminary, confidential, proprietary-- acer laboratories inc. m512x : mega i/o controller with pnp page 48 07-02-1997 document number: 512xds02.doc acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, roc tel: 886-(02) 762-8800 fax: 762-6060 table 4-24 result pha se termination values with no error last id information at result phase mt hd sector track head sector b/s 0 0 < eot nc nc s + 1 nc 0 0 = eot t + 1 nc 1 nc 0 1 < eot nc nc s + 1 nc 0 1 = eot t + 1 nc 1 nc 1 0 < eot nc nc s + 1 nc 1 0 = eot nc 1 1 nc 1 1 < eot nc nc s + 1 nc 1 1 = eot t + 1 0 1 nc eot = end of track sector number from command phase nc = no change in value s = sector number last operated on by controller t = track number programmed in command phase 4.6.2 read-deleted-data this command is the same as the read-data command except for how it handles a deleted data mark. if a deleted data mark is read, the sector is read normally. if a regular data mark is found and the sk bit is set, the sector is not read, bit 6 of st2 (control mark) is set, and the next sector is searched for. if a regular data mark is found and the sk bit is not set, the sector is read, bit 6 of st2 (control mark) is set, and the read terminates with a normal termination. 4.6.3 write-data the write-data command is very similar to the read-data command except that data is transferred from the cpu to the disk rather than the other way around. if the controller detects the write-protect signal, bit 1 of st1 (not writable) is set and an abnormal termination is indicated. 4.6.4 write-deleted-data this command is the same as the write-data command except that a deleted-data mark is written at the beginning of the data field instead of the normal data mark. 4.6.5 read a track this command is similar to the read-data command except for the following: the controller starts at the index hole and reads the sectors in their physical order, not their logical order. even though the controller reads sectors in their physical order, it still compares the header id bytes with the data programmed in the command phase. the exception to this is the sector number. internally, this is set to one, then incremented for each successive sector read. whether or not the programmed address field matches that read from the disk, the sectors are still read in their physical order. if a header id comparison fails, bit 2 of st1 (no data) is set, but the operation continues. if there is a crc error in the address or data field, the read also continues. the command terminates when it has read the number of sectors programmed in the eot parameter. 4.6.6 read id this command causes the controller to read the first address field it finds. the result phase contains the header bytes that are read. there is no data transfer during the execution phase of this command. an interrupt is generated when the execution phase is completed. 4.6.7 format-a-track this command formats one track on the disk. after the index hole is detected, data patterns are written on the disk including all gaps, address marks, address fields, and data fields. the exact details of the number of bytes for each field is controlled by the parameters given in the format-a- track command, and the iaf (index address field) bit in the mode command. the data field consists of the fill-byte specified in the command, repeated to fill the entire sector. to allow for floppy formatting, the cpu must supply the four address field bytes (track, head, sector, number of bytes) for each sector formatted during the execution phase. in other words, as the controller formats each sector, it requests four bytes through either dma requests or interrupts. this allows for non-sequential sector interleaving. table 4-29 shows some typical values for the programmable gap size. the format command terminates when the index hole is detected a second time, at which point an interrupt is generated. only the first three status bytes in the result phase are significant.
acer laboratories inc. --preliminary, confidential, proprietary-- m512x : mega i/o controller with pnp 07-02-1997 document number: 512xds02.doc page 49 acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, r.o.c. tel: 886-(02) 762-8800 fax: 762-6060 table 4-25a gap length for various sector sizes and disk types sector sector sector format* size code eot gap gap mode (dec) (dec) (hex) (hex) (hex) 8-inch drives (360 rpm, 500 kb/s) fm 128 00 1a 07 1b 256 01 0f 0e 2a 512 02 08 1b 3a 1024 03 04 47 8a 2048 04 02 c8 ff 4096 05 01 c8 ff mfm 256 01 0f 0e 36 512 02 0f 1b 54 1024 03 08 35 74 2048 04 04 99 ff 4096 05 02 c8 ff 8192 06 01 c8 ff 5.25-inch drives (300 rpm, 250 kb/s) fm 128 00 12 07 09 128 00 10 10 19 256 01 08 18 30 512 02 04 46 87 1024 03 02 c8 ff 2048 04 01 c8 ff mfm 256 01 12 0a 0c 256 01 10 20 32 512 02 08 2a 50 1024 03 04 80 f0 2048 04 02 c8 ff 4096 05 01 c8 ff 3.5-inch drives (300 rpm, 250 kb/s) fm 128 00 0f 07 1b 256 01 09 0e 2a 512 02 05 1b 3a mfm 256 01 0f 0e 36 512 02 09 1b 54 1024 03 05 35 74 table 4-25b format table for pc-compatible diskette media sector sector sector format* media size code eot gap gap type (dec) (hex) (hex) (hex) (hex) 360 k 512 02 09 2a 50 1.2 m 512 02 0f 1b 54 720 m 512 02 09 1b 50 1.44 m 512 02 12 1b 6c 2.88 m 512 02 24 1b 54 * format gap is the gap length used only for the format command.
--preliminary, confidential, proprietary-- acer laboratories inc. m512x : mega i/o controller with pnp page 50 07-02-1997 document number: 512xds02.doc acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, roc tel: 886-(02) 762-8800 fax: 762-6060 i b m f o r m a t m f m i n d e x p u l s e g a p 0 8 0 o f f f s y n c 1 2 o f 0 0 g a p 0 8 0 o f 4 e s y n c 1 2 o f 0 0 3 o f c 2 * f c i a m g a p 1 5 0 o f 4 e s y n c 1 2 o f 0 0 t r a c k h e a d s e c t o r # b y t e s c r c g a p 2 2 2 o f 4 e s y n c 1 2 o f 0 0 g a p 3 p r o g r a m m a b l e f b o r f 8 d a t a g a p 4 c r c a m 3 o f a 1 * f e a m 3 o f a 1 * g a p 1 3 2 o f 4 e s y n c 1 2 o f 0 0 t r a c k h e a d s e c t o r # b y t e s c r c g a p 2 2 2 o f 4 e s y n c 1 2 o f 0 0 g a p 3 p r o g r a m m a b l e f b o r f 8 d a t a g a p 4 c r c a m 3 o f a 1 * f e a m 3 o f a 1 * m f m m f m i s o f o r m a t i n d e x a d d r e s s f i e l d a d d r e s s f i e l d d a t a f i e l d r e p e a t e d f o r e a c h s e c t o r 3 o f c 2 * f c 3 o f c 2 * f c i a m g a p 1 5 0 o f 4 e s y n c 1 2 o f 0 0 t r a c k h e a d s e c t o r # b y t e s c r c g a p 2 4 1 o f 4 e s y n c 1 2 o f 0 0 g a p 3 p r o g r a m m a b l e f b o r f 8 d a t a g a p 4 c r c a m 3 o f a 1 * f e a m 3 o f a 1 * p e r p e n d i c u l a r f o r m a t figure 4-4 ibm, perpendicular, and iso formats supported by the format command 4.6.8 scan commands the scan commands allow data read from the disk to be compared against data sent from the cpu. there are three scan commands to choose from: scan equal disk data = cpu data scan less than or equal disk data < cpu data scan greater than or equal disk data > cpu data each sector is interpreted with the most significant byte first. if the wildcard mode is enabled from the mode command, an ffh from either the disk or cpu is used as a "don't care" byte that always matches equal. if each sector is read, the desired condition has not been met, and the next sector is read. the next sector is defined as the current sector number plus the sector step-size specified. the scan command continues until the scan condition has been met, or the end of track sector number has been reached, or if tc is asserted. if the sk bit is set, sectors with deleted data marks are ignored. if all sectors read are skipped, the command terminates with d3 of st2 set (scan equal hit). table 4-30 shows the result phase of the command. table 4-30 scan command termination values status register command d2 d3 conditions scan equal 0 1 disk = cpu 1 0 disk <> cpu scan low 0 1 disk = cpu or equal 0 0 disk < cpu 1 0 disk > cpu scan high 0 1 disk = cpu or equal 0 0 disk < cpu 1 0 disk > cpu 4.6.9 seek there are two ways to move the disk drive head to the desired track number. the first method is to enable the implied seek mode. this way, each individual read or write command automatically moves the head to the track specified in the command.
acer laboratories inc. --preliminary, confidential, proprietary-- m512x : mega i/o controller with pnp 07-02-1997 document number: 512xds02.doc page 51 acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, r.o.c. tel: 886-(02) 762-8800 fax: 762-6060 the second method is by using the seek command. during the execution phase of the seek command, the track number to seek for is compared with the present track number, and a step pulse is produced to move the head one track closer to the desired track number. this is repeated at the rate specified by the specify command until the head reaches the correct track. at this point, an interrupt is generated and a sense-interrupt command is required to clear the interrupt. during the execution phase of the seek command, the only indication via software that a seek command is in progress is bits 0~3 (drive busy) of the main status register. bit 4 of the main status register (command in progress) is not set. while the internal micro-engine is capable of multiple seeks on two or more drives at the same time since the drives are selected via the drive-control register in software, software should ensure that only one drive performs the seek command at one time. no other command except the sense-interrupt command is issued while a seek command is in progress. if the extended track range mode is enabled, write a fourth byte in the command phase to indicate the four most significant bits of the desired track number. otherwise, write only three bytes. 4.6.10 relative seek the relative seek command steps the selected drive in or out a given number of steps. this command will step the read/write head an incremental number of tracks from the current track number, contrasting to step it to the desired track number as seek command. the relative seek parameters are defined as follows: dir: read/write head step direction control 0=step head out, 1=step head in rtn: relative track number. this value will determine how many incremental tracks to step the head in or out from the current track number. 4.6.11 recalibrate the recalibrate command is very similar to the seek command. it is used to step a drive head out to track zero. step pulses are produced until the track zero signal from the drive becomes true. if the track zero signal does not go before 77 step pulses are issued, an error is generated. if the extended track range mode is enabled, an error is not generated until 3,917 pulses are issued. recalibrations on more than one drive at a time should not be issued for the same reason as explained in the seek command. no other command except the sense-interrupt command should be issued while a recalibrate command is in progress. 4.6.12 sense-interrupt status an interrupt is generated by the controller when any of the following conditions occur: 1. upon entering the result phase of: a. read-data command b. read-deleted-data command c. write-data command d. write-deleted-data command e. read-a-track command f. read-id command g. format command h. scan commands 2. during data transfers in the execution phase while in the non-dma mode 3. internal ready signal changes state (only occurs immediately after a hardware or software reset). 4. seek or recalibrate command termination an interrupt generated for reasons 1 and 2 above occurs during normal command operations and are easily recognized by the cpu. during an execution phase in non- dma mode, bit 5 (execution mode) in the msr is set to 1. upon entering result phase, this bit is set to 0. reasons 1 and 2 do not require the sense interrupt status command. the interrupt is cleared by reading or writing information to the data register. interrupts caused by reasons 3 and 4 are identified with the aid of the sense interrupt status command. this command resets the interrupt when the command byte is written. table 4-31 shows how to identify the cause of the interrupt by using bits 5, 6 and 7 of st0. issuing a sense-interrupt status command without an interrupt pending is treated as an invalid command. if the extended track range mode is enabled, a third byte should be read in the result phase which indicates the four most significant bits of the present track number. otherwise, only two bytes should be read.
--preliminary, confidential, proprietary-- acer laboratories inc. m512x : mega i/o controller with pnp page 52 07-02-1997 document number: 512xds02.doc acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, roc tel: 886-(02) 762-8800 fax: 762-6060 4.6.13 specify the specify command sets the initial values for each of the three internal timers. table 4-32 shows the timer programming values. the head-load and head-unload timers are artifacts of the upd765a. these timers determine the delay from loading the head until a read or write command is started, and unloading the head sometime after the command was completed. since the m512x head-load signal is now the software-controlled motor lines in the drive-control register, these timers only provide some delay from the initialization of a command until it is actually started. similar to the dp8474, extend these timers setting the tmr bit in the mode command. the step-rate time defines the time interval between adjacent step pulses during a seek, implied-seek, or recalibrate command. the times stated in table 4-32 are affected by the data rate. these values are for 500 kb/s mfm (250 kb/s fm) and 1 mb/s mfm (500 kb/s fm). for 300 kb/s mfm data rate (150 kb/s fm), these values, multiply by 1.6667, and for 250 kb/s mfm (125 kb/s fm) double these values. the choice of dma or non-dma operation is made by the non-dma bit. when this bit is 1, the non-dma mode is selected, and when this bit is 0, dma mode is selected. this command does not generate an interrupt. table 4-31 status register 0 termination codes interrupt code seek end d7 d6 d5 cause 1 1 0 internal ready went true 0 0 1 normal seek termination 0 1 1 abnormal seek termination table 4-32 step, head, load and unload timer definitions (500 kb/s mfm) mode 1 mode 2 timer value range value range unit step rate (16 - n) 1~16 (16 - n) 1~16 ms head unload n x 16 0~240 n x 512 0~7680 ms head load n x 2 0~254 n x 32 0~4064 ms 4.6.14 sense drive status this two-byte command obtains the status of a disk drive. status register 3 is returned in the result phase and contains the drive status. this command does not generate an interrupt. 4.6.15 verify the verify command is used to verify the data stored on a disk. this command acts exactly like a read data command except that no data is transferred to the host. data is read from the disk and crc is computed and checked against the previously stored value. 4.6.16 version the version command can be used to determine the floppy controller being used. the result phase uniquely identifies the floppy controller version. the fdc returns a value of 90h in order to be compatible with the 82077. for older version compatible with nec765 controller, a value of 80h (invalid command) will return. 4.6.17 dumpreg the dumpreg command is designed to support system run-time diagnostics and application software development and debug. the command returns important information regarding the status of many of the programmed field in the fdc. this can be used to verify the values initialized in the fdc.
acer laboratories inc. --preliminary, confidential, proprietary-- m512x : mega i/o controller with pnp 07-02-1997 document number: 512xds02.doc page 53 acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, r.o.c. tel: 886-(02) 762-8800 fax: 762-6060 4.6.18 configure the configure command controls some operation modes of the controller. it should be issued during the initialization of the fdc after power up. these bits are set to their default values after a hardware reset. eis: enable implied seek. when eis=1, the fdc will perform a seek operation before executing a read/write command. the default value is 0 (no implied seek). efifo: enable fifo. when efifo=1, the fifo is disabled (nec765a compatible mode). this means data is transferred on a byte by byte basis. the default value is 1 (fifo disable). poll: disable polling. when poll=1, polling of the drives is disabled. poll defaults to 0 (polling enable). when enabled, a single interrupt is generated after reset. fifothr: the fifo threshold in the execution phase of a read/write command. this is programmable from 1 to 16 bytes. fifothr defaults to 00. a 00h selects one byte and 0fh selects 16 bytes. pretrk: precompensation start track number. programmable from track 0 to 255. pretrk defaults to track 0. a 00h selects track 0 and a ffh selects track 255. 4.6.19. powerdown mode the powerdown mode command allows the automatic power management. the use of the command can extend the battery life in portable pc applications. to enable auto powerdown the command may be issued during the bios power on self test (post). dly: minimum powerup timer. this bit is active only if apd bit is enabled. set this bit to 0 assigns a 10msec timer, and to 1 assigns a 0.5sec timer. the timer will be re-initialized after a command execution is finished (idle state) and start to countdown. when the timer is expired, the fdc will enter the powerdown state automatically. apd: enable auto powerdown. when set to 1, the auto powerdown is enabled. 4.6.20 lock the lock command allows the user full control of the fifo parameters after a software reset. if the lock bit is set to 1, then the efifo, fifothr and pretrk bits in the configure command are not affected by a software reset. after the command byte is written, the result byte must be read before continuing to the next command. 4.6.21 invalid if an invalid command (illegal opcode byte in the command phase) is received by the controller, the controller responds with st0 in the result phase. the controller does not generate an interrupt during this condition. the system reads an 80h from st0 indicating an invalid command was received. 4.6.22 perpendicular mode the perpendicular mode command is designed to support the perpendicular recording disk drives (4mbytes unformatted capacity). the perpendicular mode command configures each of the four logical drives as a perpendicular or conventional disk drive. configuration of the four logical disk drives is done via the d3-d0 bits, or with the gap and wg control bits. this command should be issued during the initialization of the floppy controller. a 0 written to dn sets drive n to conventional mode, and a 1 sets drive n to perpendicular mode. also, the ow bit offers additional control. when ow=1, changing the values of d3- d0 is enabled. when ow=0, the internal values of d3-d0 are unaffected, regardless of what is written to d3-d0. the function of the dn bits must also be qualified by setting both wg and gap to 0. if wg and gap are not set to 00, they overrides whatever is programmed in the dn bits. table 4-4 below indicates the operation of the fdc based on the values of gap and wg. d3-d0 are unaffected by a software reset, but wg and gap are both cleared to 0 after a software reset. a hardware reset resets all the bits to zero. table 4-4 effects of wg and gap bits gap wg mode gap2 length during format portion of gap2 re-written by write data command 0 0 conventional 22 bytes 0 bytes 0 1 perpendicular (500kbps) 22 bytes 19 bytes 1 0 reserved (conventional) 22 bytes 0 bytes 1 1 perpendicular (1mbps) 41 bytes 38 bytes
--preliminary, confidential, proprietary-- acer laboratories inc. m512x : mega i/o controller with pnp page 54 07-02-1997 document number: 512xds02.doc acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, roc tel: 886-(02) 762-8800 fax: 762-6060 4.7 parallel port mode fdc in this mode, the floppy disk control signals are available on the parallel port pins. when this mode is selected, the parallel port is not available. there are four modes of operation. these modes can be selected in index 0xf1 of fdc configuration space. the fdc signals are multiplexed onto the parallel port pins as shown in table below. 0xf1[1:0] parallel port function 0 0 printer 0 1 printer 1 0 fdc(drive 0 or 1) 1 1 fdc(drive 1) the fdc signals are multiplexed onto the parallel port pins as shown in table below. conn pin no. chip pin no. spp mode type fdc mode pin direction 1 144 stbj i/o ds0j o 2 138 pd0 i/o indexj i 3 137 pd1 i/o trk0j i 4 136 pd2 i/o wpj i 5 135 pd3 i/o rdataj i 6 134 pd4 i/o dskchgj i 7 133 pd5 i/o 8 132 pd6 i/o mtr0j o 9 131 pd7 i/o 10 129 ackj i ds1j o 11 128 busy i mtr1j o 12 127 pe i wdataj o 13 126 slct i wgatej o 14 143 afdj i/o densel o 15 142 errj i hdselj o 16 141 initj i/o dirj o 17 140 slinj i/o stepj o
acer laboratories inc. --preliminary, confidential, proprietary-- m512x : mega i/o controller with pnp 07-02-1997 document number: 512xds02.doc page 55 acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, r.o.c. tel: 886-(02) 762-8800 fax: 762-6060 section 5 : serial port registers each of the serial ports function as data input/output interface in a microcomputer system. the system software determines the functional configuration of the uarts via a tri-state 8-bit bi-directional data bus. the uarts are completely independent and perform serial- to-parallel conversion on data characters received from a peripheral device or a modem, and parallel-to-serial conversion on data characters received from the cpu. the cpu can read the complete status of any of the uarts at any time during the functional operation. status information reported includes the type and condition of the transfer operations performed by the uart, as well as any error conditions (parity, overrun, framing, or break interrupt). the uarts have programmable baud rate generator capable of dividing the timing reference clock input by divisors of 1 to (2 16 - 1), and producing a 16 x clock for driving the internal transmitter logic. provisions are also included to use this 16 x clock to drive the receiver logic. the uarts have complete modem-control capability and a processor-interrupt system. interrupts can be programmed to the user's requirements, minimizing the computing required to handle communications link. table 5-1 lists the register addresses a2 ~ a0 (aen is equal to zero). dlab is the divisor latch access bit. table 5-1 serial port registers register address access (aen=0) abbreviation register name access base + dlab 0h 0 thr transmit holding register w 0h 0 rbr receiver buffer register r 0h 1 dll divisor latch lsb r/w 1h 1 dlm divisor latch msb r/w 1h 0 ier interrupt enable register r/w 2h - iir interrupt identification register r 2h - fcr fifo control register w 3h - lcr line control register r/w 4h - mcr modem control register r/w 5h - lsr line status register r 6h - msr modem status register r 7h - scr scratch pad register r/w
--preliminary, confidential, proprietary-- acer laboratories inc. m512x : mega i/o controller with pnp page 56 07-02-1997 document number: 512xds02.doc acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, roc tel: 886-(02) 762-8800 fax: 762-6060 table 5-2 register summary for each uart channel bit no. 0 1 2 3 4 5 6 7 0 dlab=0 receiver buffer register (read only) r b r data bit 0 (note 1) data bit 1 data bit 2 data bit 3 data bit 4 data bit 5 data bit 6 data bit 7 0 dlab=0 transmitter holding register (write only) t h r data bit 0 data bit 1 data bit 2 data bit 3 data bit 4 data bit 5 data bit 6 data bit 7 1 dlab=0 interrupt enable register i e r enable received data available interrupt (erdai) enable transmitter holding register empty interrupt (ethrei) enable receiver line status interrupt (elsi) enable modem status interrupt (emsi) 0 0 0 0 2 interrupt ident. register (read only) ii r ? 0 ? if interrupt pending interrupt id bit interrupt id bit 0 0 0 fifo enable fifo enable 2 fifo control register (write only) f c r fifo enable rcvr fifo reset xmit fifo reset reserved reserved reserved rcvr trigger (lsb) rcvr trigger (msb) 3 line control register l c r word length select bit 0 (wls0) word length select bit 1 (wls1) number of stop bits (stb) parity enable (pen) even parity select (eps) stick parity set break divisor latch access bit (dlab) 4 modem control register m c r data terminal ready (dtr) request to send (rts) out 1 (note 3) irq enable (note 3) loop 0 0 0 5 line status register l s r data ready (dr) overrun error (oe) parity error (pe) framing error (fe) break interrupt (bi) transmitte r holding register (thre) transmitte r empty (temt) note 2 error in rcvr fifo 6 modem status register m s r delta clear to send (dcts) delta data set ready (ddsr) trailing edge ring indicator (teri) delta data carrier detect (ddcd) clear to send (cts) data set ready (dsr) ring indicator (ri) data carrier detect (dcd) 7 scratch register (note 4) s c r bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 0 dlab=1 divisor latch (ls) d l l bit 0 bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 1 dlab=1 divisor latch (ms) d l m bit 8 bit 9 bit 10 bit 11 bit 12 bit 13 bit 14 bit 15 note : 1. bit 0 is the least significant bit. it is the first bit serially transmitted or received. 2. when operating in the xt mode, this bit will be set any time that the transmitter shift register is empty. 3. this bit no longer has a pin associated with it. 4. when operating in the xt mode, this register is not available.
acer laboratories inc. --preliminary, confidential, proprietary-- m512x : mega i/o controller with pnp 07-02-1997 document number: 512xds02.doc page 57 acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, r.o.c. tel: 886-(02) 762-8800 fax: 762-6060 5.1 line control register (lcr) the system programmer uses this read/write register to specify the format of the asynchronous data communications exchange and set the divisor latch access bit. table 5-3 lcr registers bit function 7 divisor latch access bit (dlab). 1 = to access divisor latches of the baud generator or the alternate function register during a re ad or write operation. 0 = to access any other register. 6 break control bit. this bit causes a break condition to be transmitted to the receiving uart. 1 = serial output (sout) is forced to the spacing logic 0 = break is disabled this bit acts only on sout and has no effect on transmitter logic. this enables the cpu to alert a terminal in a computer communications system. if the following sequence is followed, no erroneous or extraneous characters are transmitted because of the break : 1. load all 0s, pad character in response to thre. 2. set break after the next thre. 3. wait for the transmitter to be idle, (temt = 1), and clear break when normal transmission has to be restored. during the break, the transmitter can be used as a character timer to accurately establish the break duration. 5 stick parity bit. when parity is enabled, it is used in conjunction with bit 4 to select, mark or space parity. 1 = enable stick parity 0 = disable stick parity 4 pari ty select bit. selects either an odd or even number of 1's to be transmitted/checked in the data word bit and parity bit. 0 = odd number of 1's (parity bit is a logic 1, mark parity) 1 = even number of 1's (parity bit is a logic 0, space parity) 3 parity enable bit. the parity bit is used to produce an even or odd number of 1's when the data bits and the parity bit are added. a parity bit is generated (transmit data) or checked (received data) between the last data bit and the stop bit of the serial data. 0 = parity bit is not generated/checked 1 = parity bit is generated/checked 2 specifies the number of stop bits transmitted with each serial character. the receiver checks the first stop bit only, regardless of the number of stop bits selected. 0 = 1 stop bit 1 = 1.5 stop bits, when a 5-bit data length is selected 1 = 2 stop bits, when 6-, 7-, or 8-bit data length is selected 0-1 specify the number of data bits (data length) in each transmitted or received serial character . the following are the bit values: 00 = 5 bits 01 = 6 bits 10 = 7 bits 11 = 8 bits
--preliminary, confidential, proprietary-- acer laboratories inc. m512x : mega i/o controller with pnp page 58 07-02-1997 document number: 512xds02.doc acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, roc tel: 886-(02) 762-8800 fax: 762-6060 5.2 programmable baud generator the uart contains two independently programmable baud generators. the 24-mhz crystal oscillator frequency input is divided by 13, resulting in a frequency of 1.8462-mhz. this is sent to each baud generator and divided by the divisor for the associated uart. the output frequency of the baud generator is 16 x the baud rate, [divisor # = (frequency input) / (baud rate x 16)]. the output of each baud generator drives the transmitter and receiver sections of the associated serial channel. two 8-bit latches per channel store the divisor in a 16-bit binary format. these divisor latches must be loaded during initialization to ensure proper operation of the baud generator. upon loading either of the divisor latches, a 16-bit baud counter is loaded. table 5-5 provides decimal divisors to use with crystal frequencies of 24-mhz. the oscillator input to the chip should always be 24-mhz to ensure that the fdc timing is accurate and that the uart divisors are compatible with existing software. using a divisor of zero is not recommended. 5.3 line status register (lsr) this register provides status information to the cpu concerning the data transfer. lsr is intended for read operations only. writing to this register is not recommended as this operation is only used for factory testing. table 5-4 line status register function definition bit function 7 in 16450 mode, this bit is set to 0. in fifo, lsr7 is set when there is at least one parity error, framing error or break indication in the fifo lsr7 is cleared when the cpu reads the lsr, if there are no subsequent errors in the fifo. 6 this bit changes its function depending on whether the device is operating in xt/at mode. when in the at mode, this bit is the transmitter empty (temt) indicator. it is set to 1 whenever the transmitter holding register (thr) and the transmitter shift register (tsr) are both empty. it is reset to 0 whenever either the thr or tsr contains a data character. 5 transmitter holding register empty (thre) indicator. it indicates that the uart is ready to accept a new character for transmission. it also causes the uart to issue an interrupt to the cpu when the thre interrupt enable is set high. it is set to 1 when a character is transferred from the thre into tsr. it is reset to 0 whenever the cpu loads the thre. 4 break interrupt (bi) indicator. it is set to 1 when the received data input is h eld in the spacing (logic 0) state for longer than a full word transmission time (that is, the total time of start bit data bits parity stop bits). it is reset whenever the cpu reads the contents of the lsr. restarting after a break is received requires the sin pin to be logical 1 for at least 1/2-bit time. 3 framing error (fe) indicator. this bit indicates that the received character did not have a valid stop bit. it is set to 1 whenever the stop bit following the last data bit or parity bit is a logic 0 (spacing level). the fe indicator is reset whenever the cpu reads the contents of lsr. the uart tries to resynchronize after a framing error. to do this, it assumes that the fe was due at the next start bit, so it samples this start bit twice and then takes in the data. 2 parity error (pe) indicator. this bit indicates that the received data character does not have the correct even or odd parity, as selected by the even-parity-select bit. it is set to 1 upon detection of a parity error and reset to 0 whenever the cpu reads the contents of the lsr. 1 overrun error (oe) indicator. it indicates that data in the rbr was not read by the cpu before the next data was transferred into the rbr, thereby destroying the previous data. it is set to 1 upon detection of an overrun condition and reset to 0 whenever the cpu reads the contents of the lsr. 0 receive data ready (dr) indicator. it is set to 1 whenever a complete incoming character has been received and transferred into the rbr. it is reset to 0 by reading the data in the rbr.
acer laboratories inc. --preliminary, confidential, proprietary-- m512x : mega i/o controller with pnp 07-02-1997 document number: 512xds02.doc page 59 acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, r.o.c. tel: 886-(02) 762-8800 fax: 762-6060 table 5-5 baud rates using 1.8462 mhz clock (24 mhz/13) desired baud rate divisor used to generate 16x clock c bit 5 in cr8 or 9 50 2304 0.001 x 75 1536 - x 110 1047 - x 134.5 857 0.004 x 150 768 - x 300 384 - x 600 192 - x 1200 96 - x 1800 64 - x 2000 58 0.005 x 2400 48 - x 3600 32 - x 4800 24 - x 7200 16 - x 9600 12 - x 19200 6 - x 38400 3 0.030 x 57600 2 0.16 x 115200 1 0.16 x 230400 32770 0.16 1 460800 32769 0.16 1 note : c refers to % error difference between desired and actual, except where shown otherwise, is 0.2 %. 5.4 interrupt identification register (iir) this register keeps a record of the four interrupts prioritized by the uart to reduce software overhead during data transfers. the four levels of interrupt conditions in order of priority are: receiver-line-status, received-data-ready, transmitter-holding-register-empty, and modem-status. when the cpu accesses the iir, the uart freezes all interrupts and indicates the highest priority pending interrupt to the cpu. while this cpu access is occurring, the uart records new interrupts, but does not change its current indication until the access is complete. table 5-6 interrupt identification register bit function 6~7 these two bits are set when the fifo control register bit 0 equals 1. 4~5 always '0'. 3 ln non-fifo mode, this bit is a logic 0. in fifo mode, this bit is set along with bit 2 when a timeout interrupt is pending. 1~2 identifies the highest interrupt pending. 0 used in an interrupt environment to indicate whether an interrupt condition is pending. if yes, the iir contents may be used as a pointer to the appropriate interrupt service routine. 0 = interrupt pending 1 = no interrupt pending
--preliminary, confidential, proprietary-- acer laboratories inc. m512x : mega i/o controller with pnp page 60 07-02-1997 document number: 512xds02.doc acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, roc tel: 886-(02) 762-8800 fax: 762-6060 table 5-6 interrupt control table fifo mode only interrupt id. register interrupt set and reset functions d3 d2-d1-d0 priority level interrupt type interrupt source interrupt reset control 0 0- 0- 1 - none none - 0 1- 1- 0 highest receiver line status overrun error, parity error, framing error break interrupt reading the line status register 0 1- 0- 0 second received data available received data available read receiver buffer or the fifo drops below the trigger level 1 1- 0- 0 second character timeout indication no characters have been removed from or input to the rcvr fifo during the last 4 char times and there is at least 1 char in it during this time. reading the receiver buffer register 0 0- 1- 0 third transmitter holding register empty transmitter holding register empty reading the iir register or writing the transmitter holding register 0 0- 0- 0 fourth modem status clear to send or data set ready reading the modem status register 5.5 interrupt enable register (ier) this register enables the four types of uart interrupts. each interrupt can individually activate the ur2irqa or ur1irqa output signal. resetting bits 0 ~ 3 of the ier disables the interrupt system. similarly, setting bits of this register to 1 enables the selected interrupts. disabling an interrupt prevents it from being indicated as active in the iir and from activating the interrupt output signal. all other system functions operate in their normal manner, including the setting of the line status and modem status registers. table 5-8 interrupt enable register bit function 0 enables the received-data-available interrupt 1 enables the thre interrupt 2 enables the receiver-line-status interrupt 3 enables the modem-status interrupt 4-7 always 0 5.6 fifo control register this is a write only register at the same location as the iir (the iir is a read only register). this register is used to enable the fifos, clear the fifos, set the rcvr fifo trigger level, and select the type of dma signalling. bit 0: writing a 1 to fcr0 enables both the xmit and rcvr fifos. resetting fcr0 will clear all bytes in both fifos. when changing from fifo mode to ns16450 mode and vice versa, data is automatically cleared from the fifos. this bit must be a 1 when other fcr bits are written to or they will not be programmed. bit 1: writing a 1 to fcr1 clears all bytes in the rcvr fifo and resets its counter logic to 0. the shift register is not cleared. the 1 that is written to this bit position is self- clearing. bit 2: writing a 1 to fcr2 clears all bytes in the xmit fifo and resets its counter logic to 0. the shift register is not cleared. the 1 that is written to this bit position is self- clearing. bit 3: setting fcr3 to a 1 will cause the rxrdy and txrdy pins to change from mode 0 to mode 1 if fcr0 = 1 bit 4, 5: fcr4 to fcr5 are reserved for future use. bit 6, 7: fcr6 and fcr7 are used to set the trigger level for the rcvr fifo interrupt.
acer laboratories inc. --preliminary, confidential, proprietary-- m512x : mega i/o controller with pnp 07-02-1997 document number: 512xds02.doc page 61 acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, r.o.c. tel: 886-(02) 762-8800 fax: 762-6060 7 6 rcvr fifo trigger level (bytes) 0 0 01 0 1 04 1 0 08 1 1 14 5.7 modem control register (mcr) this register controls the interface with the modem or data set (or a peripheral emulating a modem). table 5-9 modem control register bit function 7-5 set to logic 0. 4 this bit provides a local loopback feature for the uart diagnostic testing. when set to 1, the following occurs: the transmitter serial output (sout) is set to the marking (1) state; the receiver serial input (sin) is disconnected; the output of the transmitter shift register is looped back into the receiver shift register input; the four modem control inputs (dsrj, ctsj, rij, and dcdj) are disconnected; and the dtrj, rtsj, out1, irq enable bits in mcr respectively. when operating in at mode, the modem control output pins are forced to their high (inactive) states. in the diagnostic mode, data that is transmitted is immediately received. this feature allows the processor to verify the transmit-and- receive data paths of the serial port. in the diagnostic mode, the receiver and transmitter interrupts are fully operational. the modem status interrupts are also operational, but the interrupt's sources are the lower four bits of mcr instead of the four modem control inputs. writing a 1 to any of them causes an interrupt. the interrupts are still controlled by the ier. 3 this bit enables the interrupt when set. in local loopback mode, this bit controls bit 7 of the msr. 2 this is the out1 bit. it does not have an output pin associated with it. it can be written to and read by the cpu. in local loopback mode, this bit controls bit 6 of the msr. 1 controls the rtsj output. in local loopback mode, this bit controls bit 4 of the msr. 0 controls the dtrj output. in local loopback mode, this bit controls bit 5 of the msr. 1 = dtrj output is forced to 0 0 = dtrj output is forced to 1
--preliminary, confidential, proprietary-- acer laboratories inc. m512x : mega i/o controller with pnp page 62 07-02-1997 document number: 512xds02.doc acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, roc tel: 886-(02) 762-8800 fax: 762-6060 5.8 modem status register (msr) this register gives the current state of the control lines from the modem to the cpu. the bits are set to 1 whenever a control input from the modem changes state, and set to 0 when cpu reads the msr. table 5-10 modem status register bit function 7 complement of the dcdj input. if bit 4 (loopback) of the mcr is set to 1, this bit is equivalent to irq enable in the mcr. 6 complement of the rij input. if bit 4 (loopba ck) of the mcr is set to 1, this bit is equivalent to out1 in the mcr. 5 complement of the dsrj input. if bit 4 (loopback) of the mcr is set to 1, this bit is equivalent to dtr in the mcr. 4 complement of the ctsj input. if bit 4 (loopback) of the mcr is set to 1, this bit is equivalent to rts in the mcr. 3 delta data carrier detect (ddcd) indicates that the dcdj input to the chip has changed state. whenever bit 0, 1, 2 or 3 is set to 1, a modem status interrupt is generated. 2 trailing ed ge of ring indicator (teri) detector indicates that the rij input of the chip has changed from a low to high state. 1 delta data set ready (ddsr) indicates that the dsrj input to the chip has changed its state since the last time it was read by the cpu. 0 delta clear to send (dcts) indicates that ctsj input to the chip has changed its state since the last time it was read by cpu. 5.9 scratchpad register (scr) the 8-bit read/write register does not control the uart in any way. it is intended as a scratchpad register to be used by the programmer to hold data temporarily. 5.10 infrared interface 5.10.1 sharp-ir mode this mode supports bidirectional data communication with a remote device using infrared radiation as the transmission medium. sharp-ir uses amplitude shift key (ask) and allows serial communication at baud rates up to 38.4k baud. the format of the serial data is similar to the uart data format, a zero value start bit, followed by up to 8 data bits, an optional parity bit, and ending with at least one stop bit with a binary value of one. a zero is signalled by sending a 500khz continuous pulse train of infrared radiation. a one is signalled by the absence of any infrared signal. the device operation in sharp-ir mode is similar to the operation in uart. the main difference is that the data transfer is normally performed in half duplex fashion, and the modem control and status signals are not used. selection of this mode is controlled by the ir mode bits in the uart ? s configuration space. both uart1 and uart2 can be programmed in this mode. the transfer signals will rout to sin1/sin2 and sout1/sout2. two additional pins, irrx and irtx, are also provided. 5.10.2 irda sir mode this is an operation mode similar to sharp-ir. the irda 1.0 sir allows serial communication at baud rates up to 115.2k baud. the data format is the same as sharp-ir mode except no parity bit is needed. a zero is signalled by sending a single infrared pulse. a one is signalled by not sending any pulse. the width of each pulse is 3/16ths of a single bit time. the device operation in irda 1.0 sir mode is similar to the operation in uart. the main difference is that the data transfer is normally performed in half duplex fashion, and the modem control and status signals are not used. selection of this mode is controlled by the ir mode bits in the uart ? s configuration space. both uart1 and uart2 can be programmed in this mode. the transfer signals will rout to sin1/sin2 and sout1/sout2. two additional pins, irrx and irtx, are also provided.
acer laboratories inc. --preliminary, confidential, proprietary-- m512x : mega i/o controller with pnp 07-02-1997 document number: 512xds02.doc page 63 acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, r.o.c. tel: 886-(02) 762-8800 fax: 762-6060 section 6 : keyboard controller and real time clock functional description 6.1 keyboard and rtc isa interface the m512x isa interface is functionally compatible with the m8042 style host interface. it consists of the d0-d7 data bus; the iorj, iowj and the status register, input data register, and output data register. table below shows how the interface decodes the control signals. in addition to the above signals, the host interface includes keyboard and mouse irq ? s. isa i/o address map isa address block function 0x70 (r/w) rtc address register (70h) 0x71 (r/w) rtc data register (71h) isa address niow nior block function (note 1) 0x60 0 1 kdata keyboard data write (c/d=0) (60h) 1 0 kdata keyboard data read (60h) 0x64 0 1 kdctl keyboard command write (c/d=1) (64h) 1 0 kdctl keyboard status read (64h) note 1 : these registers consist of three separate 8-bit registers. status, data/command write and data read. 6.2 keyboard controller the universal keyboard controller uses an m8042 microcontroller cpu cord. this section concentrates on the m512x enhancements to the m8042. kirq mirq gate a20 rc reset kdat kclk mclk mdat p24 p25 p21 p20 m8042 p27 p10 p26 st0 p23 tst1 p22 p11 ls05 keyboard and mouse interface kirq is the keyboard irq mirq is the mouse irq p21 is the cio14 alternate function, can be used for gate a20. p20 can be used to optionally rc reset.
--preliminary, confidential, proprietary-- acer laboratories inc. m512x : mega i/o controller with pnp page 64 07-02-1997 document number: 512xds02.doc acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, roc tel: 886-(02) 762-8800 fax: 762-6060 keyboard data write this is an 8 bit write only register. when written, the c/d status bit of the status register is cleared to zero and the ibf bit is set. keyboard data read this is an 8 bit read only register. if enabled by ? enable flags ? , the kirq output is cleared and the obf flag in the status register is cleared. if not enabled, the kirq and/or auxobf1 must be cleared in software. keyboard command write this is an 8 bit write only register. when written, the c/d status bit of the status register is set to one and the ibf bit is set. keyboard status read this is an 8 bit read only register. refer to the description of the status register for more information. cpu-to-host communication the heart of m512x can write to the output data register via register dbb. a write to this register automatically sets bit 0 (obf) in the status register. see table below host interface flags m8042 instruction flag out dbb set obf, and, if enabled, the kirq output signal goes high host-to-cpu communication the host system can send both commands and data to the input data register. the cpu differentiates between commands and data by reading the value of bit 3 of the status register. when bit 3 is ? 1 ? , the cpu interprets the register contents as a command. when bit 3 is ? 0 ? , the cpu interprets the register contents as data. during a host write operation, bit 3 is set to ? 1 ? if sa2 = 1 or reset to ? 0 ? if sa2 = 0. kirq if ? en flags ? has been executed and p24 is set to a one: the obf flag is gated onto kirq. the kirq signal can be connected to system interrupt to signify that the m512x cpu has written to the output data register via ? out dbb, a ? . if p24 is set to a zero, kirq is forced low. at power- up, after a valid reset pulse has been delivered to the device, kirq is reset to 0. kirq normally reflects the status of ? dbb ? . if ? enflags has not been executed: kirq can be controlled by writing to p24. writing a zero to p24 forces kirq low, a high forces kirq high. mirq if ? en flags ? has been executed and p25 is set to a one: ibf is inverted and gated onto mirq. the mirq signal can be connected to system interrupt to signify that the m512x cpu has read the dbb register. if ? enflags has not been executed : mirq and is controlled by p25. writing a zero to p25 forces mirq low, a high forces mirq high. (mirq is normally selected as irq12 for mouse support.) gate a20 a general purpose p21 can be routed out to the common i/o pin cio14 for use as a software controlled gate a20 or user defined output.
acer laboratories inc. --preliminary, confidential, proprietary-- m512x : mega i/o controller with pnp 07-02-1997 document number: 512xds02.doc page 65 acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, r.o.c. tel: 886-(02) 762-8800 fax: 762-6060 external keyboard and mouse interface industry-standard pc-at compatible keyboards employ a two-wire, bi-directional ttl interface for data transmission. several sources also supply ps/2 mouse products that employ the same type of interface. to facilitate system expansion, the m512x provides four signal pins that may be used to implement this interface directly for an external keyboard and mouse. the m512x has four high-drive, open-drain output (1), bidirectional port pins that can be used for external serial interfaces, such as isa external keyboard and ps/2-type mouse interfaces. they are kclk, kdat, mclk and mdat. p26 is inverted and output as kclk. the kclk pin is connected to testo. p27 is inverted and output as kdat. the kdat pin is connected to p70. p23 is inverted and output as mclk. the mclk pin is connected to test1. p22 is inverted and output as mdat. the mdat pin is connected to p11. note : external pull-ups may be required. keyboard power management the keyboard provides support for two power saving modes: soft power down mode and hard power down mode. in soft power down mode, the clock to the alu is stopped but the timer/counter and interrupts are still active. in hard power down mode, the clock to the m8042 is stopped. efforts are made to reduce power wherever possible. soft power down mode this mode is entered by executing a halt instruction. the execution of program code is halted until either reset is driven active or a data byte is written to the dbbin register by a master cpu. if this mode is exited using the interrupt, and the ibf interrupt is enabled, then program execution resumes with a call to the interrupt routine, otherwise the next instruction is executed. if it is exited using reset, then a normal reset sequence is initiated and program execution starts from program memory location 0. hard power down mode this mode is entered by executing a stop instruction. the oscillator is stopped by disabling the oscillator driver cell. when either reset is driven active or a data byte is written to the dbbin register by a master cpu, the mode will be exited (as above). however, as the oscillator cell will require an initialization time, either reset must be held active for sufficient time to allow the oscillator to stabilize. program execution will resume as above. interrupts the m512x provides the two m8042 interrupts. ibf and the timer/counter overflow. memory configurations the m512x provides 2k of on-chip rom and 256 bytes of on-chip ram. register definitions host i/f data register the input data register and, output data register, are each 8 bits wide. a write to this 8 bit register will load the keyboard data read buffer, set the obf flag and set the kirq output if enabled. a read of this register will read the data from the keyboard data or command write buffer and clear the ibf flag. refer to the kirq and status register descriptions for more information. host i/f status register the status register is 8 bits wide. table below shows the contents of the status register. status register d7 d6 d5 d4 d3 d2 d1 d0 ud ud ud ud c/d ud ibf obf this register is cleared on a reset. this register is read- only for the host and read/write by the m512x.
--preliminary, confidential, proprietary-- acer laboratories inc. m512x : mega i/o controller with pnp page 66 07-02-1997 document number: 512xds02.doc acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, roc tel: 886-(02) 762-8800 fax: 762-6060 ud writable by m512x. these bits are user- definable. c/d (command data) this bit specifies whether the input data register contains data or a command (0 = data, 1 = command). during a host data/command write operation, this bit is set to ? 1 ? if sa2 = 1 or reset to ? 0 ? if sa2 = 0. ibf (input buffer full) this flag is set to 1 whenever the host system writes data into the input data register. setting this flag activates the m512x ? s nibf (mirq) interrupt if enabled. when the m512x reads the input data register (dbb), this bit is automatically reset and the interrupt is cleared. there is no output pin associated with this internal signal. obf (output buffer full) this flag is set to 1 whenever the m512x writes to the output data register (dbb). when the host system reads the output data register, this bit is automatically reset. default reset conditions the m512x has one source of reset: an external reset via the reset pin. refer to table of resets below for the effect of each type of reset on the internal registers. resets description hardware reset (reset) kclk weak high kdat weak high mclk weak high mdat weak high host i/f data reg n/a host i/f status reg ooh nc : no change n/a : not applicable
acer laboratories inc. --preliminary, confidential, proprietary-- m512x : mega i/o controller with pnp 07-02-1997 document number: 512xds02.doc page 67 acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, r.o.c. tel: 886-(02) 762-8800 fax: 762-6060 command byte bit definition bit 7 6 5 4 3 2 1 0 rsv ibmpcc ibmpc diskbc inhovr flag rsv enobfi msb lsb command byte bit definition bit number bit definition 7 reserved. this bit should be 0. 6 ibm personal computer compatibility mode. writing a 1 to this bit tells the keyboard controller that it needs to convert the scan codes received from the keyboard to those used by the ibm pc. 5 ibm personal computer mode. writing a 1 to this bit signals the keyboard controller not to check parity, or convert scan codes. 4 disable keyboard. writing a 1 to this bit disables keyboard i/f by driving the clock-line low. 3 inhibit override. writing a 1 to this bit disables the keyboard- inhibit function. 2 system flag. the m8042 places the value written to this bit in the system flag bit of its status register. 1 reserved. this bit should be 0 . 0 enable output-buffer-full interrupt. writing a 1 to this bit causes the controller to generate an interrupt when it places data into its output buffer.
--preliminary, confidential, proprietary-- acer laboratories inc. m512x : mega i/o controller with pnp page 68 07-02-1997 document number: 512xds02.doc acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, roc tel: 886-(02) 762-8800 fax: 762-6060 status register bit definition bit 7 6 5 4 3 2 1 0 pe rto xto inh sw command data flag ibf obf msb lsb status register bit definition bit number bit definition 7 parity error. 0 : the last byte of received data had odd parity. 1 : the last byte of received data had even parity. 6 receive time-out. 0 : no error 1 : the keyboard started a transmission but did not finish within a specific receive time-out-delay. 5 transmit time-out 0 : no error 1 : the keyboard started a transmission but was not properly completed. 4 inhibit switch 0 : keyboard is inhibited 1 : keyboard is not inhibited 3 command/data byte select 0 : data byte 1 : command byte 2 system flag. this bit is set to 0 during power-on 1 input buffer full 0 : keyboard controller input buffer is empty 1 : data has been written into the buffer 0 output buff er full 0 : keyboard controller output buffer is empty 1 : keyboard controller output buffer has placed data into
acer laboratories inc. --preliminary, confidential, proprietary-- m512x : mega i/o controller with pnp 07-02-1997 document number: 512xds02.doc page 69 acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, r.o.c. tel: 886-(02) 762-8800 fax: 762-6060 commands ? description command description 20h read keyboard controller's command byte . the keyboard controller puts the command byte in its output buffer, available at i/o port 60h. 60h write keyboard controller's command byte . the next byte from the system at i/o port 60h is placed as the controller command. a1h output controller version number . a single byte of the controller's version comes at i/o port 60h. aah self test . this commands the controller to do internal diagnostics tests. a hex 55 is placed in the output buffer if no errors are detected. abh interface test . this command checks the clocks and data lines of the keyboard. 00: no errors detected 01: clock is stuck low 02: clock is stuck high 03: data is stuck low 04: data is stuck high adh disable keyboard . it disables the keyboard clock line, and also sets the corresponding bit in the command byte. it resumes after giving any keyboard command. aeh enables keyboard . it enables the keyboard clock line, and also resets the corresponding bit in the command byte. d0h read output port . this command places the output port (p2) status of the controller at i/o port 60h. d1h write output port . data following this command is loaded onto the controller's output port. e0h read test inputs . this makes the current status of the test inputs of the controller's kbc and kbd available to the system at i/o port 60h as bit 0 and bit 1, respectively. f0h ~ ffh pulse output port . bits 0 ~ 3 of the controller's output port may be pulsed low for a period of approximately 6 seconds. the same bits of the command itself indicate the bits to be pulsed. a 0 indicates that the bits should be pulsed, a 1 indicates that the bits should not be modified.
--preliminary, confidential, proprietary-- acer laboratories inc. m512x : mega i/o controller with pnp page 70 07-02-1997 document number: 512xds02.doc acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, roc tel: 886-(02) 762-8800 fax: 762-6060 6.3 real time clock this rtc super cell is a complete time of day clock with alarm and one hundred year calendar, a programmable periodic interrupt and a programmable square wave generator. n time of day register descriptions the processor program obtains time and calendar information by reading the appropriate locations. the program may initialize the time, calendar, and alarm by writing to these ram locations. the contents of the 10 time, calendar and alarm bytes may either be binary or binary-coded decimal. table below shows the binary and bcd formats of the 10 time, calendar and alarm locations. time, calendar and alarm data modes address function decimal range binary mode bcd mode 00 seconds 0-59 $0-$3b $0-$59 01 seconds alarm 0-59 $0-$3b $0-$59 02 minutes 0-59 $0-$3b $0-$59 03 minutes alarm 0-59 $0-$3b $0-$59 04 hours 1-12 0-23 $1-$c(am) $81-$8c(pm) $0-$17 $1-$12(am) $81-$92(pm) $0-$23 05 hours alarm 1-12 0-23 $1-$c(am) $81-$8c(pm) $0-$17 $1-$12(am) $81-$92(pm) $0-$23 06 day of week 1-7 $1-$7 $1-$7 07 date 1-31 $1-$1f $1-$31 08 month 1-12 $1-$c $1-$12 09 year 0-99 $0-$63 $0-$99
acer laboratories inc. --preliminary, confidential, proprietary-- m512x : mega i/o controller with pnp 07-02-1997 document number: 512xds02.doc page 71 acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, r.o.c. tel: 886-(02) 762-8800 fax: 762-6060 n address map the memory consists of 242 general purpose ram bytes, 10 ram bytes which normally contain the time, calendar, alarm data, and four control and status bytes. all 256 bytes are directly readable and writable by the processor program except for the following: 1) registers c and d are read only. 2) bit 7 of register a is read only and 3) the high order bit of the seconds byte is read only. the contents of four control and status registers (a, b, c, and d) are described in registers. n set operation before initialization of the internal registers of the m512x, the set bit in register b should be set to a 1 to prevent rtc from updating. the cpu then initializes the first ten locations in the selected format (binary or bcd). the set bit should then be cleared to allow updating. after initialization and enabling, the m512x will perform clock calendar updates in the selected data mode. n bcd and binary format the 24/12 bit in register b determines whether the hour locations will be updated using a 1-12 or 0-23 format. after initialization, the 24/12 bit cannot be changed without reinitializing the hour locations. in 12 hour format, the high order bit of the hours byte indicates pm when it is a 1. n alarm operation the three alarm bytes may be used in two ways. first, when the program inserts an alarm time in the appropriate hours, minutes, and seconds alarm locations, the alarm interrupt is initiated at the specified time each day if the alarm enable bit is high. the second usage is to insert a "don't care" state in one or more of three alarm bytes. the "don't care" code is in any byte from c0h to ffh. an alarm interrupt each hour is created with "don't care" code in the hours alarm location. similarly, an alarm is generated every minute with "don't care" codes in the hours and minutes alarm bytes. the "don't care" codes in all three alarm bytes create an interrupt every second. n interrupts the rtc plus ram includes three separate fully automatic sources of interrupts to the processor. the alarm interrupt maybe programmed to occur at rates from one-per-second to one-a-day. the periodic interrupt maybe selected for rates from half-a-second to 30.517s. the update ended interrupt maybe used to indicate to the program that an update cycle is completed. the processor program selects which interrupts, if any, it wishes to receive. three bits in register b enable the three interrupts. writing a 1 to an interrupt enable bit permits that interrupt to be initiated when the event occurs. a 0 in the interrupt enable bit prohibits the irq pin from being asserted due to the interrupt cause. if an interrupt flag is already set when the interrupt becomes enable, the irq pin is immediately activated, though the interrupt initiating the event may have occurred much earlier. thus, there are cases where the program should clear such earlier initiated interrupts before first enabling new interrupts. n divider control the divider control bits have three uses, as shown in table below. three usable operating time bases may be selected. the divider chain maybe held reset, which allows precision setting of the time. when the divider is changed from reset to an operating time base, the first update cycle is one-half second later. divider configurations divider bits osc1 frequency dv2 dv1 dv0 mode 4.194304 mhz 0 0 0 operate 1.048576 mhz 0 0 1 operate 32.768 mhz 0 1 0 operate any 1 1 * divider reset
--preliminary, confidential, proprietary-- acer laboratories inc. m512x : mega i/o controller with pnp page 72 07-02-1997 document number: 512xds02.doc acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, roc tel: 886-(02) 762-8800 fax: 762-6060 n periodic interrupt selection the periodic interrupt allows the irqj pin to be triggered from once every 30.517s. the periodic interrupt is separate from the alarm interrupt which maybe outputted from once-per-second to once-per-day. table below shows that the periodic interrupt rate is selected with the same register a bits which select the square-wave frequency. periodic interrupt rate table rs value 4.194304 mhz or 1.048576 mhz time base 32.768 khz time base 0h none none 1h 30.517 s 3.90625 ms 2h 61.035 s 7.8125 ms 3h 122.070 s 122.070 s 4h 244.141 s 244.141 s 5h 488.281 s 488.281 s 6h 976.562 s 976.562 s 7h 1.953125 ms 1.953125 ms 8h 3.90625 ms 3.90625 ms 9h 7.8125 ms 7.8125 ms ah 15.625 ms 15.625 ms bh 31.25 ms 31.25 ms ch 62.5 ms 62.5 ms dh 125 ms 125 ms eh 250 ms 250 ms fh 500 ms 500 ms n update cycle the rtc executes an update cycle one-per-second, assuming one of the proper time bases is in place, the dv2-dv0 divider is not clear, and the set bit in register b is clear. the set bit in the 1 state permits the program to initialize the time and calendar bytes by stopping an existing update and preventing a new one from occurring. the primary function of the update cycle is to increment the second byte, check for overflow, increment the minutes byte when appropriate and so forth through to the year of the century byte. the update cycle also compares each alarm byte with the corresponding time byte and issues an alarm if a match or if a "don't care" code (11xxxxxx) is present in all three positions. with a 4.194304 mhz or 1.048576 mhz time base, the update cycle takes 248s while a 32.768 khz time base update cycle takes 1984 s. during the update cycle, the time, calendar and alarm bytes are not accessible by the processor program. the rtc protects the program from reading transitional data. this protection is provided by switching the time, calendar and alarm portion of the ram off the microprocessor bus during the entire update cycle. if the processor reads these ram locations before the update is complete, the output will be undefined. the update in progress (uip) status bit is set during the interval. three methods of accommodating non-availability during update are usable by the program. in discussing the three methods, it is assumed that at random points user programs are able to call a subroutine to obtain the time of day. the first method of avoiding the update cycle uses the update ended interrupt. if enabled, an interrupt occurs after every update cycle which indicates that over 999 ms are available to read valid time and date information. before leaving the interrupt service routine, the irqf bit in register c should be cleared. the second method uses the update in progress bit (uip) in register a to determine if the update cycle is in progress or not. the uip bit will pulse once-per-second. after the uip bit goes high, the update cycle begins 244 s later. therefore, if a low is a read in the uip bit, the user has at least 244s before the time/calendar data will be changed. if a 1 is read in the uip bit, the time/calendar data may not be valid. the user should avoid interrupt service routines that would cause the time needed to read valid time/calendar data to exceed 244s.
acer laboratories inc. --preliminary, confidential, proprietary-- m512x : mega i/o controller with pnp 07-02-1997 document number: 512xds02.doc page 73 acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, r.o.c. tel: 886-(02) 762-8800 fax: 762-6060 the third method uses a periodic interrupt to determine if an update cycle is in progress. the uip bit in register a is set high between the setting of the pf bit in register c. to properly setup the internal counters for daylight savings time operation, the user must set the time at least two seconds before the roll-over will occur. likewise, the time must be set at least two seconds before the end of the 29th or 30th day of the month. n register description the rtc has four registers which are accessible to the processor program. the four registers are also fully accessible during the update cycle. register 0ah index register port : 70h data register port : 71h index : 0ah (read/write except uip) 7 6 5 4 3 2 1 0 uip dv dv1 dv0 rs3 rs2 rs1 rs0 bits 3-0 . the four rate selection bits select one of 15 taps on the 22-stage divider, or disable the divider output. the tap selected may be used to generate an output square wave (sqw pin) and/or a periodic interrupt. the program may do one of the following 1) enable the interrupt with the pie bit, 2) enable the sqw output pin with the sqwe bit, 3) enable both at the same time at the same rate, or 4) enable neither. table 7 lists the periodic interrupt rates and the square wave frequencies that may be chosen with the rs bits. these four bits are read/write bits which are not affected by resetj. bits 6-4 . three bits are used to permit the program to select various conditions of the 22 stage divider chain. the divider selection bits identify which of the three time- base frequencies is in use. table 6 shows that time bases of 4.194304 mhz, 1.048576 mhz, and 32.768 khz may be used. the divider selection bits are also used to reset the divider chain. when the time/calendar is first initialized, the program may start the divider at the precise time stored in the ram. when the divider reset is removed, the first update cycle begins one-half second later. these three read/write bits are not affected by reset. bit 7 . the update in progress (uip) bit is a status flag that maybe monitored by the program. when uip is a "1", the update cycle is in progress or will begin. when uip is a "0", the update cycle is not in progress and will not be for at least 244s (for all time bases). the time, calendar, and alarm information in ram is fully available to the program when the uip bit is zero - it is not in transition. the uip bit is a read-only bit, and is not affected by reset. writing the set bit in register b to a "1" inhibits any update cycle and then clears the uip status bit.
--preliminary, confidential, proprietary-- acer laboratories inc. m512x : mega i/o controller with pnp page 74 07-02-1997 document number: 512xds02.doc acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, roc tel: 886-(02) 762-8800 fax: 762-6060 register 0bh index register port : 70h data register port : 71h index : 0bh (read/write) 7 6 5 4 3 2 1 0 set pie aie uie sqwe dm 24/12 dse bit 0 . the daylight savings enable (dse) bit is a read/write bit which allows the program to enable two special updates (when dse is a "1"). on the last sunday of april, the time increments from 1:59:59 am to 3:00:00 am. on the last sunday of october when the time first reaches 1:59:59 am, it changes to 1:00:00 am. these special updates do not occur when the dse bit is a "0". dse is not changed by any internal operations or rest. bit 1 . the 24/12 control bit establishes the format of the hours bytes as either the 24-hour mode (a "1") or the 12- hours mode (a "0"). this is a read/write bit, which is affected only by software. bit 2 . the data mode (dm) bit indicates whether time and calendar updates are to use binary or bcd formats. the dm bit is written by the processor program and may be read by the program, but is not modified by any internal functions or reset. a "1" in dm signifies binary data, while a "0" in dm specifies binary-coded decimal (bcd) data. bit 3 . when the square-wave enable (sqwe) bit is set to a "1" by the program, a square-wave signal at the frequency specified in the rate selection bits (rs3 to rs0) appears on the sqw pin. when the sqwe bit is set to a zero, the sqw pin is held low. the state of sqwe is cleared by the resetj pin. sqwe is a read/write bit. bit 4 . the uie (update-ended interrupt enable) bit is a read/write bit which enables the update-end flag (uf) bit in register c to assert irq. the resetj pin going low or the set bit going high clears the uie bit. bit 5 . the alarm interrupt enable (aie) bit is a read/write bit which when set to a "1" permits the alarm flag (af) bit in register c to assert irq. an alarm interrupt occurs for each second that the three time bytes and the three alarm bytes (including a "don't care" alarm code of binary 11xxxxxx). when the aie bit is a "0", the af bit does not initiate an irq signal. the resetj pin clears aie to "0". the internal functions do not affect the aie bit. bit 6 . the periodic interrupt enable (pie) bit is read/write bit which allows the periodic-interrupt flag (pf) bit in register c to cause the irq pin to be driven low. a program writes a "1" to the pie bit in order to receive periodic interrupts at the rate specified by the rs3, rs2, rs1, and rs0 bits in register a. a zero in pie blocks irq from being initiated by a periodic interrupt, but the periodic flag (pf) bit is still set at the periodic rate. pie is not modified by any internal ks82c6818a functions, but is cleared to "0" by a resetj. bit 7 . when the set bit is a "0", the update cycle functions normally by advancing the counts once-per- second. when the set bit is written to a "1", any update cycle in progress is aborted and the program may initialize the time and calendar bytes without an update occurring in the midst of initializing. set is a read/write bit which is not modified by reset or internal functions of the m512x.
acer laboratories inc. --preliminary, confidential, proprietary-- m512x : mega i/o controller with pnp 07-02-1997 document number: 512xds02.doc page 75 acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, r.o.c. tel: 886-(02) 762-8800 fax: 762-6060 register 0ch index register port : 70h data register port : 71h index : 0ch (read only) 7 6 5 4 3 2 1 0 irqf pf af uf 0 0 0 0 bits 3-0 . the unused bits of status register c are read as 0's and cannot be written. bit 4 . the update-ended interrupt flag (uf) bit is set after each update cycle. when the uie bit is a "1", the "1" in uf causes the irqf bit to be a "1", asserting irq, uf is cleared by a register c read or a resetj. bit 5 . a "1" in the af (alarm interrupt flag) bit indicates that the current time has matched the alarm time. a "1" in the af causes the irq pin to go low, and a "1" to appear in the irqf bit, when the aie bit also is a "1". a reset or a read of register c clears af. bit 6 . the periodic interrupt flag (pf) is a read-only bit which is set to a "1" when a particular edge is detected on the selected tap of the divider chain. the rs3 to rs0 bits establish the periodic rate. pf is set to a "1" independent of the state of the pie bit. pf being a "1" initiates and irq signal and sets the irqf bit when pie is also a "1". the pf bit is cleared by a /reset/ or a software read of register c. bit 7 . the interrupt request flag (irqf) is set to a "1" when one or more of the following are true : pf = pie = "1" af = aid = "1" uf = aie = "1" any time the irqf bit is a "1", the irq pin is driven low. all flag bits are cleared after register c is read by the program when the reset pin is low. register 0dh index register port : 70h data register port : 71h index : 0dh (read only) 7 6 5 4 3 2 1 0 vrt 0 0 0 0 0 0 0 bits 6-0 . the remaining bits of register d are unused. they cannot be written, but are always read as 0's. bit 7 . the valid ram and time (vrt) bit indicates the condition of the contents of the ram, provided the vbat is satisfactorily connected. a "0" appears in the vrt bit when the vbat is low. the processor program can set the vrt bit when the time and calendar are initialized to indicate that the ram and time are valid. the vrt is a read only bit which is not modified by the resetj pin. the vrt bit can only be set by reading register d.
--preliminary, confidential, proprietary-- acer laboratories inc. m512x : mega i/o controller with pnp page 76 07-02-1997 document number: 512xds02.doc acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, roc tel: 886-(02) 762-8800 fax: 762-6060 section 7 : bios 7.1 bios buffer the m512x contains one 245 type buffer that can be used for a bios buffer. if the bios buffer is not used, then romcsj and romoej must be tied high so as not to interfere with the boot rom. this function allows data transmission from the rd bus to the sd bus or from the sd bus to the rd bus. the direction of the transfer is controlled by romoej. the enable input, romcsj, can be used to disable the transfer and isolate the buses. romcsj romoej l l rd [0:7] data to sd [0:7] bus l h sd [0:7] data to rd [0:7] h x isolation m5123 sd[7:0] romcsj romoej bios
acer laboratories inc. --preliminary, confidential, proprietary-- m512x : mega i/o controller with pnp 07-02-1997 document number: 512xds02.doc page 77 acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, r.o.c. tel: 886-(02) 762-8800 fax: 762-6060 section 8 : parallel port 8.1 parallel port interface the m512x incorporates one ibm xt/at compatible parallel port. the m512x supports the optional ps/2 type bi- directional parallel port (spp), the enhanced parallel port (epp) and the extended capabilities port (ecp) parallel port modes. please refer to the configuration description (section 3) for information on disabling, power down, changing the base address of the parallel port, and selecting the mode of operation. the m512x also incorporates a protective circuitry, which prevents possible damage to the parallel port due to printer power-up. the functionality of the parallel port is achieved through the use of eight addressable ports with their associated registers and control gating. the control and data port are read/write by the cpu, the status port is read/write in the epp mode. the address map of the parallel port is shown below: data port base address + 00h status port base address + 01h control port base address + 02h epp addr port base address + 03h epp data port 0 base address + 04h epp data port 1 base address + 05h epp data port 2 base address + 06h epp data port 3 ba se address + 07h the bit map of these registers : table 8-1 bit mapped registers data port d0 d1 d2 d3 d4 d5 d6 d7 note pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 1 status port tmout 0 oslc errj slct pe ackj busyj 1 control port strobe autofd initj slc irqe pcd 0 0 1 epp addr port pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 2, 3 epp data port 0 pd0 pd1 pd2 dp3 pd4 pd5 pd6 pd7 2, 3 epp data port 1 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 2, 3 epp data port 2 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 2, 3 epp data port 3 pd0 pd1 pd2 pd3 pd4 pd5 pd6 pd7 2, 3 note 1: these registers are available in all modes. 2: these registers are only available in epp mode. 3: for epp mode, iochrdy must be connected to the isa bus.
--preliminary, confidential, proprietary-- acer laboratories inc. m512x : mega i/o controller with pnp page 78 07-02-1997 document number: 512xds02.doc acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, roc tel: 886-(02) 762-8800 fax: 762-6060 table 8-2 parallel port connector host connector pin no. standard epp ecp 1 77 strobej writej strobej 2-9 71-68, 66-63 pdata <0:7> pdata<0:7> pdata<0:7> 10 62 ackj intr ack 11 61 busy waitj busy,periphack(3) 12 60 pe (nu) perror, nackreverse(3) 13 59 select (nu) select 14 76 autofdj dstrbj autofd, hostack(3) 15 75 errorj (nu) fault(1) periphrequest(3) 16 74 initj (nu) init(1) reverserqst(3) 17 73 selectinj astrbj selectin(1,3) (1) = compatible mode (3) = high speed mode note : for the cable interconnection required for ecp support and the slave connector pin numbers, please refer to the ieee 1284 extended capabilities port protocol and isa standard , rev. 1.09, jan. 7, 1993. this document is available from microsoft. 8.2 ibm xt/at compatible, bi-directional and epp modes data port address offset = 00h the data port is located at an offset of '00h' from the base address. the data register is cleared at initialization by reset. during a write operation, the data register latches the contents of the data bus with the rising edge of the iowj input. the contents of this register are buffered (non inverting) and output onto the pd0 -pd7 ports. during a read operation in spp mode, pd0 - pd7 ports are buffered (not latched) and output to the host cpu. status port address offset = 01h the status port is located at an offset of '01h' from the base address. the contents of this register are latched for the duration of an iorj read cycle. the bits of the status port are defined as follows: bit 0 tmout - time out this bit is valid in epp mode only and indicates that a 10 sec time out has occurred on the epp bus. a logic 0 means that no time out error has occured; a logic 1 means that a time out error has been detected. this bit is cleared by a reset. writing a one to this bit clears the time out status bit. on a write, this bit is self clearing and does not require a write of a zero. writing a zero to this bit has no effect. bits 1, 2 - are not implemented as register bits. during a read of the printer status register, these bits are at low level. bit 3 errj - errorj the level on the errorj input is read by the cpu as bit 3 of the printer status register. a logic 0 means an error has been detected; a logic 1 means no error has been detected. bit 4 slct - printer selected status the level on the slct input is read by the cpu as bit 4 of the printer status register. a logic 1 means the printer is on line; a logic 0 means it is not selected. bit 5 pe - paper end the level on the pe input is read by the cpu as bit 5 of the printer status register. a logic 1 indicates a paper end; a logic 0 indicates the presence of paper. bit 6 ackj - acknowledgej the level on the ackj input is read by the cpu as bit 6 of the printer status register. a logic 0 means that the printer has received a character and can now accept another. a logic 1 means that it is still processing the last character or has not received the data. bit 7 busyj - busyj the complement of the level on the busy input is read by the cpu as bit 7 of the printer status register. a logic 0 in this bit means that the printer is busy and cannot accept a new character. a logic 1 means that it is ready to accept the next character.
acer laboratories inc. --preliminary, confidential, proprietary-- m512x : mega i/o controller with pnp 07-02-1997 document number: 512xds02.doc page 79 acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, r.o.c. tel: 886-(02) 762-8800 fax: 762-6060 control port address offset = 02h the control port is located at an offset of ? 02h ? from the base address. the control register is initialized by the reset input, bits 0 to 5 only being affected; bits 6 and 7 are hard wired low. bit 0 strobe - strobe this bit is inverted and output onto the strobej output. bit 1 autofd - autofeed this bit is inverted and output onto the autofdj output. a logic 1 causes the printer to generate a line feed after each line is printed. a logic 0 means no autofeed. bit 2 initj - initiate outputj this bit is output onto the initj output without inversion. bit 3 slctin - printer select input this bit is inverted and output onto the slctinj output. a logic 1 on this bit selects the printer; a logic 0 means the printer is not selected. bit 4 irqe - interrupt request enable the interrupt request enable bit when set to a high level may be used to enalbe interrupt requests from the parallel port to the cpu. an interrupt request is generated on the irq port by a positive going ackj input. when the irqe bit is programmed low the irq is disabled. bit 5 pcd - parallel control direction parallel control direction is valid in extended mode only (crc<7> = 0). in printer mode, the direction is always out regardless of the state of this bit. in bi-directional mode, a logic 0 means that the printer port is in output mode (write); a logic 1 means that the printer port is in input mode (read). bits 6 and 7 during a read are a low level, and cannot be written. epp address port address offset = 03h the epp address port is located at an offset of ? 03h ? from the base address. the address register is cleared at initialization by reset. during a write operation, the contents of db0-db7 are buffered (non inverting) and output onto the pdo - pd7 ports, the leading edge of iowj causes an epp address write cycle to be performed, the trailing edge of iow latches the data for the duration of the epp write cycle. during a read operation, pdo -pd7 ports are read, the leading edge of ior causes an epp address read cycle to be performed and the data output to the host cpu, the deassertion of addrstb latches the pdata for the duration of the ior cycle. this register is only available in epp mode. epp data port 0 address offset = 04h the epp data port 0 is located at an offset of ? 04h ? from the base address. the data register is cleared at initialization by reset. during a write operation, the contents of db0-db7 are buffered (non-inverting) and output onto the pd0 - pd7 ports, the leading edge of iowj causes an epp data write cycle to be performed, the trailing edge of iow latches the data for the duration of the epp write cycle. during a read operation, pd0- pd7 ports are read, the leading edge of ior causes an epp read cycle to be performed and the data output to the host cpu, the deassertion of datastb latches the pdata for the duration of the ior cycle. this register is only available in epp mode. to maintain compatibility with intel ? s 82360sl device that has 32-bit host bus interface, four consecutive byte address locations (data port 0~4) are provided for transferring data. epp data port 1 address offset = 05h the epp data port 1 is located at an offset of ? 05h ? from the base address. please refer to epp data port 0 for a description of operation. this register is only available in epp mode. epp data port 2 address offset = 06h the epp data port 2 is located at an offset of ? 06h ? from the base address. please refer to epp data port 0 for a description of operation. this register is only available in epp mode. epp data port 3 address offset = 07h the epp data port 3 is located at an offset of ? 07h ? from the base address. please refer to epp data port 0 for a description of operation. this register is only available in epp mode. epp operation when the epp mode is selected in the configuration register, the standard and bi-directional modes are also available. if no epp read, write or address cycle is currently executing, then the pdx bus is in the standard or bi-directional mode, and all output signals (strobe, autofd, init) are as set by the spp control port and direction is controlled by pcd of the control port. in epp mode, the system timing is closely coupled to the epp timing. for this reason, a watchdog timer is required to prevent system lockup. the timer indicates if more than 10 usec have elapsed from the start of the epp cycle (iorj or iowj asserted) waitj will be deasserted. if a time-out occurs, the current epp cycle is aborted and the time-out condition is indicated in status bit 0.
--preliminary, confidential, proprietary-- acer laboratories inc. m512x : mega i/o controller with pnp page 80 07-02-1997 document number: 512xds02.doc acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, roc tel: 886-(02) 762-8800 fax: 762-6060 epp mode version 1.7 timing sd7-0 iowj iorj writej (strobj) dstrbj(auto fdj/slctinj)/ astrbj pd7-0 waitj(busy) iochrdy the timing for a write/read epp 1.7 operation is shown in timing diagram above the sequence of operation is : epp 1.7 data/address write epp 1.7 data/address read 1. the host writes a byte to data (address) port. iowj goes low to drive data to pd7-0. 1. the host reads a byte from data (address) port. iorj goes low to input data from pd7-0. 2. the epp pulls writej low to indicate it ? s a write cycle. 2. the epp keeps writej high to indicate it ? s a read cycle. 3. the epp pulls dstrbj (astrbj) low to signal that data is valid. 3. the epp pulls dstrbj (astrbj) low to indicate that peripheral have to start sending data. 4. if waitj goes low during the cycle, iochrdy is pulled low. 4. if waitj is low during the cycle, iochrdy is pulled low. 5. when waitj goes high, the epp pulls iochrdy high and then iowj will go high 5. when waitj goes high, the epp pulls iochrdy high and then iorj will go high 6. when iowj goes high, it pulls writej & dstrbj(astrbj) high, and then the epp can change pd7-0 6. when iorj goes high, it pulls writej & dstrbj(astrbj) high, and then the peripheral can tri- state pd7-0
acer laboratories inc. --preliminary, confidential, proprietary-- m512x : mega i/o controller with pnp 07-02-1997 document number: 512xds02.doc page 81 acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, r.o.c. tel: 886-(02) 762-8800 fax: 762-6060 epp mode version 1.9 timing sd7-0 iowj iorj writej (strobj) dstrbj(auto fdj/slctinj)/ astrbj pd7-0 waitj(busy) iochrdy epp write cycle epp read cycle the timing for a write/read epp 1.9 operation is shown in timing diagram above the sequence of write/read operation is : epp 1.9 data/address write epp 1.9 data/address read 1. the host writes a byte to data (address) port. iowj goes low to drive data to pd7-0. 1. the host reads a byte from data (address) port. iorj goes low to input data from pd7-0. 2. iochrdy goes low and waits for waitj to go low. 2. iochrdy goes low and waits for waitj to go low. 3. if waitj goes low or already low, the epp pulls or keeps writej low to show being a write cycle. 3. if waitj goes low or was already low, the epp pulls or keeps writej high to indicate being a read cycle. 4. the epp pulls dstrbj (astrbj) low to indicate that data is ready and waits for waitj to go high. 4. the epp pulls dstrbj (astrbj) low to signal the peripheral to start sending data and waits for waitj to go high. 5. when waitj goes high, it pulls iochrdy and dstrbj (astrbj) high, and then iowj will go high to turn off this cycle. 5. when waitj goes high, it pulls iochrdy and dstrbj (astrbj) high, and then iorj will go high to turn off this cycle.
--preliminary, confidential, proprietary-- acer laboratories inc. m512x : mega i/o controller with pnp page 82 07-02-1997 document number: 512xds02.doc acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, roc tel: 886-(02) 762-8800 fax: 762-6060 table 8-3 - epp pin descriptions epp signal epp name type epp description writej writej o this signal is active low. it denotes a write operation. pd<0:7> address/ data i/o bi-directional epp byte wide address and data bus. intr interrupt i this signal is active high and positive edge triggered. (pass through with no inversion, same as spp.) wait waitj i this signal is active low. it is driven inactive as a positive acknowledgement from the device that the transfer of data is completed. it is driven active as an indication that the device is ready for the next transfer. datastb data strobej o this signal is active low. it is used to denote data read or write operation. reset resetj o this signal is active low. when driven active, the epp device is reset to its initial operational mode. addrstb address strobej o this signal is active low. it is used to denote address read or write operation. pe paper end i same as spp mode. slct printer select status i same as spp mode. errj error i same as spp mode. pdir parallel port direction o this output shows the direction of the data transfer on the parallel port bus. a low means an output /write condition and a high means an input/read condition. this signal is normally a low (output/write) uniess pcd of the control register is set or if an epp read cycle is in progress. note 1 : spp and epp can use 1 common register. note 2 : writej is the only epp output that can be over-ridden by spp control port during an epp cycle. for correct epp read cycles, pcd is required to be a low. extended capabilities parallel port ecp provides a number of advantages, some of which are listed below. high performance half-duplex forward and reverse channel interlocked handshake, for fast reliable transfer optional single byte rle compression for improved throughput (64:1) channel addressing for low-cost peripherals maintains link and data layer separation permits the use of active output drivers permits the use of adaptive signal timing peer-to-peer capability pword a port word; equal in size to the width of the isa interface. for this implementation, pword is always 8 bits. 1 a high level. 0 a low level. these terms may be considered synonymous: periphclk, ackj hostack, autofdj periphack, busy periphrequestj, faultj reverserequestj, initj ackreversej, perror xflag, select ecpmode, selectinj hostclk, strobej vocabulary the following terms are used in this document: assert when a signal asserts it transitions to a "true" state, when a signal deasserts it transitions to a "false" state. forward host to peripheral communication. reverse peripheral to hose communication.
acer laboratories inc. --preliminary, confidential, proprietary-- m512x : mega i/o controller with pnp 07-02-1997 document number: 512xds02.doc page 83 acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, r.o.c. tel: 886-(02) 762-8800 fax: 762-6060 reference document ieee 1284 extended capabilities port protocol and isa interface standard , rev 1.09, jan 7, 1993. this document is available from microsoft. the bit map of the extended parallel port registers is : d7 d6 d5 d4 d3 d2 d1 d0 note data pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 ecpafifo addr/ rle address or rle field 2 dsr busyj ackj perror select faultj 0 0 0 1 dcr 0 0 direction acklnten selectin initj autofd strobe 1 cfifo parallel port data fifo 2 ecpdfifo ecp data fifo 2 tfifo test fifo 2 cnfga 0 0 0 1 0 0 0 0 cnfgb compress intrvalue 0 0 0 0 0 0 ecr mode errintren j dmaen service intr full empty note 1: these registers are available in all modes. note 2: all fifos use one common 16 byte fifo. isa implementation standard this specification describes the standard isa interface to the extended capabilities port (ecp). all isa devices supporting ecp must meet the requirements contained in this section or the port will not be supported by microsoft. for a description of the ecp protocol, please refer to the ieee 1284 extended capabilities port protocol and isa interface standard , rev. 1.09, jan. 7, 1993. this document is available from microsoft. description the port is software and hardware compatible with existing parallel ports so that it may be used as a standard lpt port if ecp is not required. the port is designed to be simple and requires a small number of gates to implement. it does not do any "protocol" negotiation, rather it provides an automatic high burst-bandwidth channel that supports dma for ecp in both the forward and reverse directions. small fifos are employed in both forward and reverse directions to smooth data flow and improve the maximum bandwidth requirement. the size of the fifo is 16 bytes deep. the port supports an automatic handshake for the standard parallel port to improve compatibility mode transfer speed. the port also supports run length encoded (rle) decompression (required) in hardware. decompression is accomplished by counting identical bytes and transmitting an rle byte that indicates how many times the next byte is to be repeated. decompression simply intercepts the rle byte and repeats the following byte the specified number of times. hardware support for compression is optional.
--preliminary, confidential, proprietary-- acer laboratories inc. m512x : mega i/o controller with pnp page 84 07-02-1997 document number: 512xds02.doc acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, roc tel: 886-(02) 762-8800 fax: 762-6060 table 8-4 ecp pin descriptions name type description strobej o during write operations strobej registers data or address into the slave on the asserting edge (handshakes with busy). pdata 7:0 i/o contains address or data or rle data. ackj i indicates valid data driven by the peripheral when asserted. this signal handshakes with autofdj in reverse. periphack (busy) i this signal deasserts to indicate that the peripheral can accept data. this signal handshakes with strobej in the forward direction. in the reverse direction this signal indicates whether the data lines contain ecp command information or data. the peripheral uses this signal to flow control in the forward direction. it is an "interlocked" handshake with strobej. periphack also provides command information in the reverse direction. perror (ack reversej) i used to acknowledge a change in the direction of the transfer (asserted= forward). the peripheral drives this signal low to acknowledge reverserequestj. it is an "interlocked" handshake with reverserequestj. the host relies upon ackreversej to determine when it is permitted to drive the data bus. select i indicates printer on line. autofdj (hostack) o requests a byte of data from the peripheral when asserted, handshaking with ackj in the reverse direction. this signal indicates whether the data lines contain ecp address or data, the host drives this signal to flow control in the reverse direction. it is an "interlocked" handshake with ackj. hostack also provides command information in the forward phase. faultj (periph requestj) i generates an error interrupt when asserted. this signal provides a mechanism or peer-to-peer communication. this signal is valid only in the forward direction. during ecp mode, the peripheral is permitted (but not required) to level this pin to request a reverse transfer. the request is merely a "hint" to the host; the host has ultimate control over the transfer direction. this signal would be typically used to generate an interrupt to the host cpu. initj o sets the transfer direction (asserted = reverse, deasserted = forward). this pin is driven low to place the channel in the reverse direction. the peripheral is only allowed to drive the bi- directional data bus while in ecp mode and hostack is low and selectlnj is high. selectlnj o always deasserted in ecp mode. register definitions the register definitions are based on the standard ibm addresses for lpt. all of the standard printer ports are supported. the additional registers attach to an upper bit decode of the standard lpt port definition to avoid conflict with standard isa devices. the port is equivalent to a generic parallel port interface and may be operated in that mode. the port registers vary depending on the mode field in the ecr. the table below lists these dependencies. operation of the devices in modes other than those specified is undefined. table 8-5 ecp register definitions name address (note 1) ecp modes function data +000h r/w 000-001 data register ecpafifo +000h r/w 011 ecp fifo (address) dsr +001h r/w all status register dcr +002h r/w all control register cfifo +400h r/w 010 parallel port data fifo ecpdfifo +400h r/w 011 ecp fifo (data) tfifo +400h r/w 110 test fifo cnfga +400h r 111 configuration register a cnfgb +401h r/w 111 configuration register b ecr +402h r/w all extended control register note 1: these addresses are added to the parallel port base address as selected by configuration register or jumpers. note 2: all addresses are qualified with aen. refer to the aen pin definition.
acer laboratories inc. --preliminary, confidential, proprietary-- m512x : mega i/o controller with pnp 07-02-1997 document number: 512xds02.doc page 85 acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, r.o.c. tel: 886-(02) 762-8800 fax: 762-6060 table 8-6 mode descriptions mode description* 000 spp mode 001 ps/2 parallel port mode 010 parallel port data fifo mode 011 ecp parallel port mode 100 epp mode (if this option is enabled in the configuration registers) 101 (reserved) 110 test mode 111 configuration mode * refer to ecr register description data and ecpafifo port address offset = 00h modes 000 and 001 (data port) the data port is located at an offset of '00h' from the base address. the data register is cleared at initialization by reset. during a write operation, the data register latches the contents of the data bus on the rising edge of the iowj input. the contents of this register are buffered (non inverting) and output onto the pd0 - pd7 ports. during a read operation, pd0 - pd7 ports are read and output to the host cpu. mode 011 (ecp fifo- address/rle) a data byte written to this address is placed in the fifo and tagged as an ecp address/rle. the hardware at the ecp port transmits this byte to the peripheral automatically. the operation of this register is only defined for the forward direction (direction is 0). refer to the ecp parallel port forward timing diagram, located in the timing diagrams section of this data sheet. device status register (dsr) address offset = 01h the status port is located at an offset of '01h' from the base address. bits 0 - 2 are not implemented as register bits, during a read of the printer status register these bits are a low level. the bits of the status port are defined as follows: bit 3 faultj the level on the fault input is read by the cpu as bit 3 of the device status register. bit 4 select the level on the select input is read by the cpu as bit 4 of the device status register. bit 5 perror the level on the perror input is read by the cpu as bit 5 of the device status register. printer status register. bit 6 ackj the level on the ackj input is read by the cpu as bit 6 of the device status register. bit 7 busyj the complement of the level on the busy input is read by the cpu as bit 7 of the device status register. device control register (dcr) address offset = 02h the control register is located at an offset of '02h' from the base address. the control register is initialized to zero by the reset input, bits 0 to 5 being affected; bits 6-7 are read as 0. bit 0 strobe - strobe this bit is inverted and output onto the strobej output. bit 1 autofd - autofeed this bit is inverted and output onto the autofdj output. a logic 1 causes the printer to generate a line feed after each line is printed. a logic 0 means no autofeed. bit 2 initj - initiate output this bit is output onto the initj output without inversion. bit 3 selectin this bit is inverted and output onto the slctinj output. a logic 1 on this bit selects the printer; a logic 0 means the printer is not selected. bit 4 acklnten - interrupt request enable the interrupt request enable bit when set to a high level may be used to enable interrupt requests from the parallel port to the cpu due to a low to high transition on the ackj input. refer to the description of the interrupt under operation, interrupts. bit 5 direction if mode = 000 or mode = 010, this bit has no effect and the direction is always out regardless of the state of this bit. in all other modes, direction is valid and a logic 0 means that the printer port is in output mode (write); a logic 1 means that the printer port is in input mode (read). bits 6 and 7 during a read are a low level, and cannot be written. cfifo (parallel port data fifo) address offset = 400h mode = 010 bytes written or dmaed from the system to this fifo are transmitted by a hardware handshake to the peripheral using the standard parallel port protocol. transfers to the fifo are byte aligned. this mode is only defined for the forward direction.
--preliminary, confidential, proprietary-- acer laboratories inc. m512x : mega i/o controller with pnp page 86 07-02-1997 document number: 512xds02.doc acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, roc tel: 886-(02) 762-8800 fax: 762-6060 ecpdfifo (ecp data fifo) address offset = 400h mode = 011 bytes written or dmaed from the system to this fifo, when the direction bit is 0, are transmitted by a hardware handshake to the peripheral using the ecp parallel port protocol. transfers to the fifo are byte aligned. data bytes from the peripheral are read under automatic hardware handshake from ecp into this fifo when the direction bit is 1. reads or dmas from the fifo will return bytes of ecp data to the system. tfifo (test fifo mode) address offset =400h mode = 110 data bytes may be read, written or dmaed to or from the system to this fifo in any direction. data in the tfifo will not be transmitted to the parallel port lines using a hardware protocol handshake. however, data in the tfifo may be displayed on the parallel port data lines. the tfifo will not stall when overwritten or underrun. if an attempt is made to write data to a full tfifo, the new data is not accepted into the tfifo. if an attempt is made to read data from an empty tfifo, the last data byte is re-read again. the full and empty bits must always keep track of the correct fifo state. the tfifo will transfer data at the maximum isa rate so that software may generate performance metrics. the fifo size and interrupt threshold can be determined by writing bytes to the fifo and checking the full and servicelntr bits. the writelntr threshold can be determined by starting with a full tfifo, setting the direction bit to 0 and emptying it a byte at a time until servicelntr is set. this may generate a spurious interrupt, but will indicate that the threshold has been reached. the readlntr threshold can be determined by setting the direction bit to 1 and filling the empty tfifo a byte at a time until servicelntr is set. this may generate a spurious interrupt, but will indicate that the threshold has been reached. data bytes are always read from the head of tfifo regardless of the value of the direction bit. for example if 44h, 33h, 22h is written to the fifo, then reading the tfifo will return 44h, 33h, 22h in the same order as was written. cnfga (configuration register a) address offset = 400h mode = 111 this register is a read only register. when read, 10h is returned. this indicates to the system that this is an 8-bit implementation. (pword = 1 byte) cnfgb (configuration register b) address offset = 401h mode = 111 bit 7 compress this bit is read only. during a read, it is a low level. this means that this chip does not support hardware rle compression. it does support hardware de-compression. bit 6 intrvalue returns the value on the isa irq line to determine possible conflicts. bits 5~0 : the ecp parallel port configuration register b must reflect the irq and drq selected by the configuration registers irq selected config.reg. b bits 5: 3 dma selected config.reg. b bits 5: 3 14 110 3 011 13 101 2 010 11 100 1 001 10 011 others 000 9 010 7 001 5 111 others 000 ecr (extended control register) address offset = 402h mode = all this register controls the extended ecp parallel port functions. bits 7, 6, 5 these bits are read/write and select the mode. bit 4 errlntrenj read/write (valid only in ecp mode) 1: disables the interrupt generated on the asserting edge of faultj. 0: enables an interrupt pulse on the high to low edge of faultj. note that an interrupt will be generated if fault is asserted (interrupting) and this bit is written from a 1 to a 0. this prevents interrupts from being lost in the time between the read of the ecr and the write of the ecr. bit 3 dmaen read/write
acer laboratories inc. --preliminary, confidential, proprietary-- m512x : mega i/o controller with pnp 07-02-1997 document number: 512xds02.doc page 87 acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, r.o.c. tel: 886-(02) 762-8800 fax: 762-6060 1: enables dma (dma starts when servicelntr is 0). 0: disable dma unconditionally. bit 2 servicelntr read/write 1: disable dma and all of the service interrupts. 0: enables one of the following 3 cases of interrupts. once one of the 3 service interrupts has occurred, servicelntr bit shall be set to a 1 by hardware, it must be reset to 0 to re- enable the interrupts. writing this bit to a 1 will not cause an interrupt. case dmaen = 1: during dma (this bit is set to a 1 when terminal count is reached). case dmaen = 0 direction = 0: this bit shall be set to 1 whenever there are writelntr threshold or more bytes free in the fifo. case dmaen = 0 direction = 1: this bit shall be set to 1 whenever there are readlntr threshold or more valid bytes to be read from the fifo. bit 1 full read only 1: the fifo cannot accept another byte or the fifo is completely full. 0: the fifo has at least 1 free byte. bit 0 empty read only 1: the fifo is completely empty. 0: the fifo contains at least 1 byte of data.
--preliminary, confidential, proprietary-- acer laboratories inc. m512x : mega i/o controller with pnp page 88 07-02-1997 document number: 512xds02.doc acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, roc tel: 886-(02) 762-8800 fax: 762-6060 table 8-7 - extended control register r/w mode 000 standard parallel port mode. in this mode, the fifo is reset and common collector drivers are used on the control lines (strobej, autofdj, initj and selectlnj). setting the direction bit will not tri-state the output drivers in this mode. 001 ps/2 parallel port mode. same as above except that direction may be used to tri-state the data lines and reading the data register returns the value on the data lines and not the value in the data register. all drivers have active pull-ups (push-pull). 010 parallel port fifo mode. this is the same as 000 except that bytes are written or dmaed to the fifo. fifo data is automatically transmitted using the standard parallel port protocol. note that this mode is only useful when direction is 0. all drivers have active pull-ups (push-pull). 011 ecp parallel port mode. in the forward direction(0), bytes placed into the ecpdfifo and bytes written to the ecpafifo are placed in a single fifo and transmitted automatically to the peripheral using ecp protocol. in the reverse direction (1), bytes are moved from the ecp parallel port and packed into bytes in the ecpdfifo. all drivers have active pull-ups (push-pull). 100 selects epp mode: in this mode, epp is selected if the epp supported option is selected in configuration register cr4. all drivers have active pull-ups (push-pull) 101 reserved 110 test mode. in this mode, the fifo may be written and read, but the data will not be transmitted on the parallel port. all drivers have active pull-ups (push-pull). 111 configuration mode. in this mode the confga, confgb registers are accessible at 0x400 and 0x401. all drivers have active pull-ups (push- pull). operation mode switching/software control software will execute p1284 negotiation and all operation prior to a data transfer phase under programmed i/o control (mode 000 or 001) hardware provides an automatic control line handshake, moving data between the fifo and the ecp port only in the data transfer phase (modes 011 or 010). setting the mode to 011 or 010 will cause the hardware to initiate data transfer. if the port is in mode 000 or 001, it may switch to any other mode. if the port is not in mode 000 or 001, it can only be switched to mode 000 or 001. the direction can only be changed in mode 001. once in an extended forward mode the software should wait for the fifo to be empty before switching back to mode 000 or 001. in this case all control signals will be deasserted before the mode switch. in an ecp reverse mode, the software waits for all the data to be read from the fifo before changing back to mode 000 or 001. since the automatic hardware ecp reverse handshake only cares about the state of the fifo, it may have acquired loose data that will be eliminated. it may in fact be in the middle of a transfer when the mode is changed back to 000 or 001. in this case the port will deassert autofdj independent of the state of the transfer. the design shall not cause glitches on the handshake signals if the software meets the constraints above. ecp operation prior to ecp operation the host must negotiate on the parallel port to determine if the peripheral supports the ecp protocol. this is a somewhat complex negotiation carried out under program control in mode 000. after negotiation, it is necessary to initialize some of the port bits. the following are required: . set direction = 0, enabling the drivers. . set strobe = 0, causing the strobej signal to default to the deasserted state. . set autofd = 0, causing the autofdj signal to default to the deasserted state. . set mode = 011 (ecp mode) ecp address/rle bytes or data bytes may be sent automatically by writing the ecpafifo or ecpdfifo respectively. note that all fifo data transfers are byte wide and byte aligned. address/rle transfers are byte-wide and only allowed in the forward direction.
acer laboratories inc. --preliminary, confidential, proprietary-- m512x : mega i/o controller with pnp 07-02-1997 document number: 512xds02.doc page 89 acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, r.o.c. tel: 886-(02) 762-8800 fax: 762-6060 the host may switch directions by first switching to mode = 001, negotiating for the forward or reverse channel, setting direction to 1 or 0, then setting mode = 011. when direction is 1 the hardware shall handshake for each ecp read data byte and attempt to fill the fifo. bytes may then be read from the ecpdfifo as long as it is not empty. ecp transfers may also be accomplished (albeit slowly) by handshaking individual bytes under program control in mode = 001, or 000. termination from ecp mode termination from ecp mode is similar to the termination from nibble/byte modes. the host is permitted to terminate from ecp mode only in specific well-defined states. the termination can only be executed while the bus is in the forward direction. to terminate while the channel is in the reverse direction, it must first be changed into the forward direction. command/data ecp mode supports two advanced features to improve the effectiveness of the protocol for some applications. the features are implemented by allowing the transfer of normal 8-bit data or 8-bit commands. when in the forward direction, normal data is transferred when hostack is high and an 8-bit command is transferred when hostack is low. the most significant bit of the command indicates whether it is a run-length count (for compression) or a channel address. when in the reverse direction, normal data is transferred when periphack is high and an 8-bit command is transferred when periphack is low. the most significant bit of the command is always zero. reverse channel addresses are seldom used and may not be supported in hardware. table 8-8 forward channel commands (hostack low) reverse channel commands (peripack low) d7 d[6:0] 0 run-length count (0-127) (mode 0011 0x00 only) 1 channel address (0-127) data compression the m512x supports run length encoded (rle) decompression in hardware and can transfer compressed data to a peripheral. run length encoded (rle) compression in hardware is not supported. to transfer compressed data in ecp mode, the compression count is written to the ecpafifo and the data byte is written to the ecpdfifo. compression is accomplished by counting identical bytes and transmitting an rle byte that indicates how many times the next byte is to be repeated. decompression simply intercepts the rle byte and repeats the following byte the specified number of times. when a run-length count is received from a peripheral, the subsequent data byte is replicated the specified number of times. a run-length count of zero specifies that only one byte of data is represented by the next data byte, whereas a run-length count of 127 indicates that the next byte should be expanded to 128 bytes. to prevent data expansion, however, run-length counts of zero should be avoided. pin definition the drivers for strobej, autofdj, initj and selectlnj are open-collector in mode 000 and are push-pull in all other modes. isa connections the interface can never stall causing the host to hang. the width of data transfers if strictly controlled on an i/o address basis per this specification. all fifo-dma transfers are byte wide, byte aligned and end on a byte boundary. (the pword value can be obtained by reading configuration register a, cnfga, described in the next section.) single byte wide transfers are always possible with standard or ps/2 mode using program control of the control signals. interrupts the interrupts are enabled by servicelntr in the ecr register. servicelntr = 1 disables the dma and all of the service interrupts. servicelntr = 0 enables the selected interrupt condition. if the interrupting condition is valid, then the interrupt is generated immediately when this bit is changed from a 1 to a 0. this can occur during programmed i/o if the number of bytes removed or added from/to the fifo does not cross the threshold. the interrupt generated is isa friendly in that it must pulse the interrupt line low, allowing for interrupt sharing. after a brief pulse low following the interrupt event, the interrupt line is tri-stated so that other interrupts may assert.
--preliminary, confidential, proprietary-- acer laboratories inc. m512x : mega i/o controller with pnp page 90 07-02-1997 document number: 512xds02.doc acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, roc tel: 886-(02) 762-8800 fax: 762-6060 an interrupt is generated when : 1. for dma transfers: when servicelntr is 0, dmaen is 1 and the dma tc is received. 2. for programmed i/o: a. when servicelntr is 0, dmaen is 0, direction is 0 and ther are writelntr threshold or more free bytes in the fifo. also, an interrupt is generated when servicelntr is cleared to 0 whenever there are writelntr threshold or more free bytes in the fifo. b. (1) when servicelntr is 0, dmaen is 0, direction is 1 and there are readlntr threshold or more bytes in the fifo. also, an interrupt is generated when servicelntr is cleared to 0 whenever there are readlntr threshold or more bytes in the fifo. 3. when nerrlntren is 0 and nfault transitions from high to low or when nerrlntren is set from 1 to 0 and nfault is asserted. 4. when acklnten is 1 and the nack signal transitions from a low to a high. fifo operation the fifo threshold is set in the chip configuration registers. all data transfers to or from the parallel port can proceed in dma or programmed i/o (non-dma) mode as indicated by the selected mode. the fifo is used by selecting the parallel port fifo mode or ecp parallel port model. (fifo test mode will be addressed separately.) after a reset, the fifo is disabled. each data byte is transferred by a programmed i/o cycle or pdrq depending on the selection of dma or programmed i/o mode. the following paragraphs detail the operation of the fifo flow control. in these descriptions, ranges from 1 to 16. the parameter fifothr, which the user programs, is one less and ranges from 0 to 15. a low threshold value (i.e.2) results in longer periods of time between service requests, but requires faster servicing of the request for both read and write cases. the host must be very responsive to the service request. this is the desired case for use with a "fast" system. a high value of threshold (i.e. 12) is used with a "sluggish" system by affording a long latency period after a service request, but results in more frequent service requests. dma transfers dma transfers are always to or from the ecpdfifo, tfifo or cfifo. dma utilizes the standard pc dma services. to use the dma transfers, the host first sets up the direction and state as in the programmed i/o case. then it programs the dma controller in the host with the desired count and memory address. lastly it sets dmaen to 1 and servicelntr to 0. the ecp requests dma transfers from the host by activating the pdrq pin. the dma will empty or fill the fifo using the appropriate direction and mode. when the terminal count in the dma controller is reached, an interrupt is generated and servicelntr is asserted, disabling dma. in order to prevent possible blocking of refresh requests dreq shall not be asserted for more than 32 dma cycles in a row. the fifo is enabled directly by asserting pdackj and addresses need not be valid. pintr is generated when a tc is received. pdrq must not be asserted for more than 32 dma cycles in a row. after the 32nd cycle, pdrq must be kept unasserted until pdackj is deasserted for a minimum of 350 nsec. ( note : the only way to properly terminate dma transfers is with a tc.) dma may be disabled in the middle of a transfer by first disabling the host dma controller. then setting servicelntr to 1, followed by setting dmaen to 0, and waiting for the fifo to become empty or full. restarting the dma is accomplished by enabling dma in the host, setting dmaen to 1, followed by setting servicelntr to 0. dma mode - transfers from the fifo to the host (note: in the reverse mode, the peripheral may not continue to fill the fifo if it turns out of data to transfer, even if the chip continues to request more data from the peripheral.) the ecp activates the pdrq pin whenever there is data in the fifo. the dma controller must respond to the request by reading data from the fifo. the ecp will deactivate the pdrq pin when the fifo becomes empty or when the tc becomes true (qualified by pdackj), indicating that no more data is required. pdrq goes inactive after pdackj goes active for the last byte of a data transfer (or on the active edge of iorj, on the last byte, if no edge is present on pdackj). if pdrq goes inactive due to the fifo going empty, then pdrq is active again as soon as there is one byte in the fifo. if pdrq goes inactive due to the tc, then pdrq is active again when there is one byte in the fifo, and servicelntr has been re-enabled. (note: a data underrun may occur if pdrq is not removed in time to prevent an unwanted cycle.)
acer laboratories inc. --preliminary, confidential, proprietary-- m512x : mega i/o controller with pnp 07-02-1997 document number: 512xds02.doc page 91 acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, r.o.c. tel: 886-(02) 762-8800 fax: 762-6060 programmed i/o mode or non-dma mode the ecp or parallel port fifos may also be operated using interrupt driven programmed i/o. software can determine the writelntrthreshold, readlntrthreshold, and fifo depth by accessing the fifo in test mode. programmed i/o transfers are to the ecpdfifo at 400h and ecpafifo at 000h or from the ecpdfifo located at 400h, or to/from the tfifo at 400h. to use the programmed i/o transfers, the host first sets up the direction and state, sets dmaen to 0 and servicelntr to 0. the ecp requests programmed i/o transfers from the host by activating the pintr point. the programmed i/o will empty or fill the fifo using the appropriate direction and mode. note : a threshold of 16 is equivalent to a threshold of 15. these two cases are treated the same. programmed i/o - transfers from the fifo to the host in the reverse direction an interrupt occurs when servicelntr is 0 and readlntr threshold bytes are available in the fifo. if at this time the fifo is full it can be emptied completely in a single burst, otherwise readlntr threshold bytes may be read from the fifo in a single burst. programmed i/o - transfers from the host to the fifo in the forward direction, an interrupt occurs when servicelntr is 0 and there are writelntrthreshold or more bytes free in the fifo. at this time if the fifo is empty it can be filled with a single burst before the empty bit need to be re-read. otherwise it may be filled with writelntrthreshold bytes. the fifo threshold value is selected via = 16 data bytes fifo, if =0 the readintr threshold = { data bytes fifo, if =1 to 15 for example, if the =4, then the serviceintr is set whenever there are 4-16 bytes in the fifo 16 free bytes fifo, if =0 the writeintr threshold = { free bytes fifo, if =1 to 15 for example, if the =4, then the serviceintr is set whenever there are 4-16 bytes free in the fifo.
--preliminary, confidential, proprietary-- acer laboratories inc. m512x : mega i/o controller with pnp page 92 07-02-1997 document number: 512xds02.doc acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, roc tel: 886-(02) 762-8800 fax: 762-6060 section 9 : common i/o ports the m512x has 22 independently programmable common i/o ports (cio). each cio port is represented as a bit in one of three 8-bit registers, cio1, cio2 or cio3. only 6 bits of cio2 are implemented. each cio port and its alternate function is listed in table below. cio port alternate function register assignment cio10 interrupt steering cio1, bit 0 cio11 interrupt steering cio1, bit 1 cio12 irrx input cio1, bit 2 cio13 irtx output cio1, bit 3 cio14 gatea20 output cio1, bit 4 cio15 rc reset output cio1, bit 5 cio16 i 2 c interface clk output cio1, bit 6 cio17 i 2 c interface data i/o cio1, bit 7 cio20 cio2, bit 0 cio21 cio2, bit 1 cio22 cio2, bit 2 cio23 cio2, bit 3 cio24 cio2, bit 4 cio25 keylock input cio2, bit 5 cio30 kbc clock source input cio3, bit 0 cio31 cs0j output cio3, bit 1 cio32 cs1j output cio3, bit 2 cio33 alt_kclk i/o cio3, bit 3 cio34 alt_kdat i/o cio3, bit 4 cio35 alt_mclk i/o cio3, bit 5 cio36 alt_mdat i/o cio3, bit 6 cio37 alt_kbc select input cio3, bit 7 cio registers cio1, cio2 and cio3 can be accessed by the host when the chip is in the normal run mode; i.e., not in the configuration mode. the host uses an index and data register to access the cio registers. the power on default index and data registers are 0xea and 0xeb respectively. when the chip is in configuration mode, these index and data registers are used to access the internal configuration registers. in configuration mode, the index address may be programmed to reside on address 0xe0, 0xe2, 0xe4 or 0xea. the data address is automatically set to the index address + 1. upon exiting the configuration mode, the new index and data registers are used to access registers cio1, cio2 and cio3. to access the cio1 register the host should first make sure the chip is in the normal (run) mode. then it should perform an iow of 0x01 to the index register (at 0xex) to select cio1 and then read or write the data register (at index+1) to access the cio1 register. to access cio2 the host should perform an iow of 0x02 to the index register and then access cio2 through the data register. to access cio3 the host should perform an iow of 0x03 to the index register and then access cio3 through the data register. register address normal (run) mode config mode index 0xe0,0xe2, 0xe4,0xea 0x01 0x02 0x03 0x00-0xff data 0xe1,0xe3, 0xe5,0xeb access to cio1 access to cio2 access to cio3 access to internal config registers cio ports can assume alternate functions such as input-type, output-type or i/o type. the cio port structure for each type is illustrated in the following figures.
acer laboratories inc. --preliminary, confidential, proprietary-- m512x : mega i/o controller with pnp 07-02-1997 document number: 512xds02.doc page 93 acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, r.o.c. tel: 886-(02) 762-8800 fax: 762-6060 common i/o configuration registers assigned to each cio port is an 8-bit cio configuration register which is used to independently program each i/o port. the cio configuration registers are only accessible when the m512x is in the configuration mode. configuration section of this specification contains more details. reading and writing cio ports when a cio port is programmed as an input, reading it through the cio register latches either the inverted or non-inverted logic value present at the cio pin; writing to it has no effect. when a cio port is programmed as an output, the logic value written into the cio register is either output to or inverted to the cio pin; when read the result will reflect the contents of the cio register bit. this is summarized in table 9-1. table 9-1 - cio read/write behavior host operation cio input port cio output port read latched value of cio pin bit value in cio register write no effect bit placed in cio register gatea20 gatea20 is an internal signal from the keyboard controller (port 21). the m512x may be configured to drive this signal onto cio14 by programming its cio configuration register. kbc rc reset kbc rc is an internal signal from the keyboard controller (port 20). the m512x may be configured to drive this signal onto cio15 by programming its cio configuration register. the m512x provides a set of flexible input/output control functions to the system designer through a set of common i/o pins (cio). these cio pins may perform simple i/o or may be individually configured to provide a predefined alternate function. power on reset configures all cio pins as simple non-inverting inputs. there are four types of cio ports as shown in following figures : d-type transparent i/o bit niow nior 0 1 cio register bit-n cio pin cio configuration register bit-1 (polarity) cio configuration register bit-0 (input/output) cio having no alternate function (cio20-cio24)
--preliminary, confidential, proprietary-- acer laboratories inc. m512x : mega i/o controller with pnp page 94 07-02-1997 document number: 512xds02.doc acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, roc tel: 886-(02) 762-8800 fax: 762-6060 d-type transparent i/o bit niow nior 0 1 cio register bit-n cio pin cio configuration register bit-1 (polarity) cio configuration register bit-0 (input/output) 1 0 alternate output function cio configuration register bit-3 (alt-function) cio having an output-type alternate function. (cio13, cio14, cio15, cio16, cio31, cio32) d-type transparent i/o bit niow nior 0 1 cio register bit-n cio pin cio configuration register bit-1 (polarity) cio configuration register bit-0 (input/output) alternate input function cio configuration register bit-3 (alt function) cio having an input-type alternate function (cio10, cio11, cio12, cio30, cio37, cio25)
acer laboratories inc. --preliminary, confidential, proprietary-- m512x : mega i/o controller with pnp 07-02-1997 document number: 512xds02.doc page 95 acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, r.o.c. tel: 886-(02) 762-8800 fax: 762-6060 d-type transparent i/o bit niow nior 0 1 cio register bit-n cio pin cio configuration register bit-1 (polarity) cio configuration register bit-0 alternate i/o function 0 1 0 1 a alt bit 3 b alt bit 3 c a b c cio having an i/o type alternate function (cio17, cio33, cio34, cio35, cio36)
--preliminary, confidential, proprietary-- acer laboratories inc. m512x : mega i/o controller with pnp page 96 07-02-1997 document number: 512xds02.doc acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, roc tel: 886-(02) 762-8800 fax: 762-6060 section 10 : electrical characteristics 10.1 absolute maximum ratings absolute maximum ratings are those values beyond which damage to the device may occur. continuous operation at these limits is not intended and should be limited to those conditions specified under dc electrical characteristics. unless otherwise specified, all voltages are measured with respect to ground. table 10-1 absolute maximum ratings item ratings supply voltage vdd -0.5v to +7v operating supply voltage 4.5v to 5.5v all input and output -0.5v to vcc +0.5v voltages with respect to vss storage temperature range (tstg) -65 o c to 150 o c operating temperature (ta) 0 o c to 70 o c package power dissipation (pd) 750 mw lead temperature (tl) 260 o c (soldering, 10 seconds) |vcc - vcca| 0.6v esd tolerance (czap) 100 pf 10.2 dc characteristics v dd = 5.0v 5%, v ss = 0v, unless otherwise specified. these values are measured under static conditions, and not under dynamic conditions. table 10-2 dc characteristics symbol parameter conditions min max unit vih high level input voltage except osc1/clk 2.0 vcc v vil low level input voltage except osc1/clk -0.5 0.8 v iin input current except osc pins, vin = vdd or gnd 1.0 ua icca average vdda vin = 2.4v or 0.5v, 10 ma supply current i/o = 0 ma* quiescent vdda supply vin = vdd or gnd, 400 ua current in low power mode i/o = 0 ma* icc average vdd vdd = 5 .5v; no loads on supply current the outputs: iorj, iowj, sin, dsrj, dcdj, ctsj, rij = 2v; all other inputs: 0.8v or 50 ma 2.4v; clk = 24 mhz; divisor = efffh quiescent vdd supply vin = vdd or gnd, current in low power mode i/o = 0 ma*
acer laboratories inc. --preliminary, confidential, proprietary-- m512x : mega i/o controller with pnp 07-02-1997 document number: 512xds02.doc page 97 acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, r.o.c. tel: 886-(02) 762-8800 fax: 762-6060 table 10-2 dc characteristics (continued) symbol parameter conditions min max unit oscillator pins (osc1/clk) iosc osc1 input current (osc1 = gnd), 1.6 ma vin = vdd or gnd vih osc1 high level input voltage osc2 = gnd 2.4 v vil os c1 low level input voltage osc2 = gnd 0.4 v disk drive interface pins (mtr0~3, dr0~3, wdata, wgate, rdata, dir, hdsel, trk0, wrtprt, rpm, step, dskchg, index) vh input hysteresis 250 typical mv vol low level output voltage iout = 36 ma 0.4 v ilkg output high leakage current vout = vdd or gnd 100 ua vih high level input voltage 2.2 v vil low level input voltage 0.8 v microprocessor and parallel port pins vol output low voltage iol = 24 ma on d0~d7; 16 ma on pd0~pd7; 16 ma on initj, afdj, stbj and 0.4 v slinj; 4 ma on all other outputs voh output high voltage ioh = -12 ma on d0~d7; -16 ma on pd0~pd7; -16 ma on initj, afdj, stbj and 2.4 v slinj; -4 ma on all other outputs iil input leakage vdd = 5.5v, vss = 0v all other pins floating 10 ua ioz output tri-state leakage vdd = 5.5v, vss = 0v vout = 0v, 5.5v 20 ua * i cc is measured with a 0.1 uf supply decoupling capacitor-to-ground. 10.2.1 capacitance t a = 25 o c , v dd = v ss = 0v) table 10-3 cap acitance symbol parameter conditions typ max units cin input capacitance fc = 1 mhz; unmeasured 5 7 pf cout output capacitance pins returned to vss 6 8 pf ci/o i/o capacitance 10 12 pf
--preliminary, confidential, proprietary-- acer laboratories inc. m512x : mega i/o controller with pnp page 98 07-02-1997 document number: 512xds02.doc acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, roc tel: 886-(02) 762-8800 fax: 762-6060 10.3 ac characteristics t a = 0 o c to +70 o c , v dd = +5v 5%. all ac timings can be met with current loads that do not exceed 3.2 ma or -8 ua at 100 pf capacitive loading. for capacitive loads that exceed 100 pf, the following typical derating factors should be used: 100 pf < c l 150 pf, t = (0.10 ns/pf) (c l - 100 pf) typical 150 pf < c l 200 pf, t = (0.08 ns/pf) (c l - 100 pf) and t = (0.5 ns/ma) (i sink ma) or t = -(0.5 ns/ma) (i source ma) t source is always negative, i sink 4.8 ma, i source -120 ua, c l 250 pf. table 10-4 lists the ac characteristics of the m512x. table 10-4 ac characteristics symbol parameter conditions min max unit tar delay from address to iorj 19 ns taw delay from address to iowj 19 ns tch duration of clock high pulse see note a 16 ns tcl duration of clock low pulse see note a 16 ns tdh data hold time 10 ns tds data setup time 19 ns thz iorj to floating data delay see note b 13 ns tra address hold time from iorj 0 ns trc read cycle update 36 ns trd iorj strobe width 60 ns ttps port setup 13 ns tri read strobe to clear irq6 52 ns trvd delay from iorj to data 31 ns trw reset pulse width 100 ns twa address hold time from iowj 0 ns twc write cycle update 36 n s twi write strobe to clear irq6 52 ns two write to output 41 ns twr iowj strobe width 50 ns rc read cycle = tar + trd + trc 115 ns wc write cycle = taw + twr + twc 105 ns note: a. external clock (24 mhz maximum). b. charge and discharge time is determined by v ol , v oh and the external loading.
acer laboratories inc. --preliminary, confidential, proprietary-- m512x : mega i/o controller with pnp 07-02-1997 document number: 512xds02.doc page 99 acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, r.o.c. tel: 886-(02) 762-8800 fax: 762-6060 10.4 ac test conditions in table 10-5, c l = 100 pf. this includes jig and scope capacitance. s1 is open for push-pull outputs. s1 is equal to v cc for high impedance to active low, and active low to high impedance measurements. s1 is equal to gnd for high impedance to active high, and active high to high impedance measurements. r l = 1.0 kohm for cpu interface pins. for the open drain drive interface pins s1 = v cc and r l = 150 ohms. table 10-5 ac test conditions input pulse levels gnd to 3.0v input rise and fall times 6 ns i/o reference levels 1.3v tri-state reference levels active high - 0.5v active low + 0.5v device under test input output c l r l 0.1 f s 1 v cc external clock input (24 mhz) 2.4v clk 0.4v 2.0v 0.8v t cl t ch the 2.4v and 0.4v levels are the voltages tthat tthe inputs are driven to during ac testing table 10-6 serial interf ace baud generator symbol parameter conditions min max unit n baud divisor 12 16 - 1 t bhd baud output positive clk = 24 mhz / 2, edge delay 100 pf load 56 ns t bld baud output negative clk = 24 mhz / 2, edge delay 100 pf load 56 ns baudoutj timing clk baudoutj baudoutj/2 baudoutj/3 baudoutj(/n,n>3) |<- n ->| ->| |<- tbld ->| |<- tbhd ->| |<- tbld ->| |<- tbhd ->| |<- tbld ->| |<- tbhd
--preliminary, confidential, proprietary-- acer laboratories inc. m512x : mega i/o controller with pnp page 100 07-02-1997 document number: 512xds02.doc acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, roc tel: 886-(02) 762-8800 fax: 762-6060 cpu interface read cycle aen a0-a9 iorj iowj d0-d7 valid data valid thz irq6 tri tar trvd tra trc trd rc write cycle aen a0-a9 iowj iorj d0-d7 irq6 valid twi taw tds twa twc twr wc valid data tdh
acer laboratories inc. --preliminary, confidential, proprietary-- m512x : mega i/o controller with pnp 07-02-1997 document number: 512xds02.doc page 101 acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, r.o.c. tel: 886-(02) 762-8800 fax: 762-6060 dma timing dma acknowledge is sufficient to acknowledge a data transfer. read or write strobes are necessary only if data is presented to the data bus. if read/write strobes are applied, then the read/write strobes and the acknowledge must be removed within 1 us of each other. table 10-7 dma timing symbol parameter min max unit t aa dak pulse width 60 ns t aq end of drq from dak 92 ns t qa dak assertion from drq 8 ns t qr drq to read or write strobe 8 ns t tq time after last drq that tc must be asserted note ns t tt tc strobe width 40 ns note: the terminal count pin (tc) terminat es the data transfer operation. there are several constraints placed on the timing of tc. 1) tc is enabled by dakj, so tc must be pulsed while dakj is low. 2) tc must occur before ((1/data rate x 8) - 1 us). data rate is the exact data transfer rate being used. drq dakj iorj or iowj tc taq taa tqa ttq ttt tqr
--preliminary, confidential, proprietary-- acer laboratories inc. m512x : mega i/o controller with pnp page 102 07-02-1997 document number: 512xds02.doc acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, roc tel: 886-(02) 762-8800 fax: 762-6060 drive read and write timing table 10-8 drive read and write timing symbol parameter conditions min unit t rdw read-data pulse-width 25 ns t wd write-data pulse-width 250 kb/s ( mfm ) 500 ns t hds head-sel ect setup to write-gate-assertion 40 us t hdh head-select hold from write-gate 12 ns 300 kb/s ( mfm ) 416 ns 500 kb/s ( mfm ) 250 ns 1000 kb/s ( mfm ) 225 ns note : whenever wgate is asserted, the wdata line is active. at the end of each write, one dummy byte is written before wgate is deasserted. >| || |< twd trdw >| |< >| thdh |< rdata hdsel wgate wdata
acer laboratories inc. --preliminary, confidential, proprietary-- m512x : mega i/o controller with pnp 07-02-1997 document number: 512xds02.doc page 103 acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, r.o.c. tel: 886-(02) 762-8800 fax: 762-6060 drive track access timing table 10-9 drive track access timing symbol parameter min max unit t dh direction hold from end-of-step 1 step time t drv dri ve-select or motor-time from write-strobe 100 ns t dst direction-setup prior to step 6 us t iw index pulse-width 100 ns t stp step pulse-width 8 us >| tdrv |< >| tdh |< >| tstp|< >| tdst |< >| programmable |< >| tiw |< >| tdrv |< index iowj dr0-3, mtr0-3 dir step
--preliminary, confidential, proprietary-- acer laboratories inc. m512x : mega i/o controller with pnp page 104 07-02-1997 document number: 512xds02.doc acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, roc tel: 886-(02) 762-8800 fax: 762-6060 transmitter table 10-10 transmitter symbol parameter min max unit t hr delay from iowj ( wr thr ) to reset interrupt 50 ns t ir delay from iorj ( rd iir ) to reset interrupt ( thre ) 50 ns t irs delay from initial intr reset to transmit start 8 24 baudout cycles t si delay from initial write to interrupt 16 24 baudout cycles t sti delay from start to interrupt ( thre ) 8 baudout cycles data (5-8) serial out interrupt iowj iorj |<- thr ->| |<- tsi ->| |<- thr ->| |<-tirs->| parity ->| |<-tsti tir ->| |<- start start
acer laboratories inc. --preliminary, confidential, proprietary-- m512x : mega i/o controller with pnp 07-02-1997 document number: 512xds02.doc page 105 acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, r.o.c. tel: 886-(02) 762-8800 fax: 762-6060 modem control table 10-11 modem control symbol parameter max unit t mdo delay from iowj ( wr mcr ) to output 50 ns t rim delay to reset interrupt from iorj ( rd msr ) 98 ns t sim delay to set interrupt from modem input 50 ns *iowj rtsj, dtrj ctsj,dsrj,dcdj interrupt **iorj rij |<-tmdo->| |<- tsim ->| |<- trim ->| |<- tmdo ->| |<- tsim ->| |<- trim ->| |<- tsim - >| * : see write cycle timing ** : see read cycle timing
--preliminary, confidential, proprietary-- acer laboratories inc. m512x : mega i/o controller with pnp page 106 07-02-1997 document number: 512xds02.doc acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, roc tel: 886-(02) 762-8800 fax: 762-6060 receiver table 10-12 receiver symbol parameter max unit t rai delay from active edge of iorj to reset interrupt 98 ns t rint delay from inactive edge of iorj ( rd lsr ) to reset interrupt 50 ns t scd delay from r clk to sample time 41 ns t sint delay from stop to set interrupt 2 baudout cycles data(5-8) sin sample clk1 rdr int. lsi int. iorj(rdrbr) iorj(rdlsr)
acer laboratories inc. --preliminary, confidential, proprietary-- m512x : mega i/o controller with pnp 07-02-1997 document number: 512xds02.doc page 107 acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, r.o.c. tel: 886-(02) 762-8800 fax: 762-6060 amplitude shift keyed ir transmit timing table 10-13. ask ir transmit timing symbol parameter min typ max unit tmo modulated output bit time us tob off bit time us tmo3 modulated output ? on ? 0.79 1 1.21 us tmo4 modulated output ? on ? 0.79 1 1.21 us tmo5 modulated output ? on ? 0.79 1 1.21 us tmo6 modulated output ? off ? 0.79 1 1.21 us 0 1 0 1 0 0 1 1 0 1 1 data irtx tob tmo mirtx tmo6 tmo5 tmo3 tmo4 notes : 1. t1, t2 timing referred to irda transmit timing @ each baud rate. 2. uart1, uart2 0xf1 bit 1: 1 = receive active low 0 = receive active high (default ) 3. mirtx are the modulated outputs. ( 500k )
--preliminary, confidential, proprietary-- acer laboratories inc. m512x : mega i/o controller with pnp page 108 07-02-1997 document number: 512xds02.doc acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, roc tel: 886-(02) 762-8800 fax: 762-6060 irda receive timing table 10-14. irda receive timing symbol parameter min typ max unit tpw1 pulse width at 115k baud 1.40 1.60 2.71 us tpw1 pulse width at 57.6k baud 1.40 3.22 3.69 us tpw1 pulse width at 38.4k baud 1.40 4.80 5.53 us tpw1 pulse width at 19.2k baud 1.40 9.70 11.07 us tpw1 pulse width at 9.6k baud 1.40 19.50 22.13 us tpw1 pulse width at 4.8k baud 1.40 39.00 44.27 us tpw1 pulse width at 2.4k baud 1.40 78.00 88.55 us tbt2 bit time at 115k baud 8.68 us tbt2 bit time at 57.6k baud 17.40 us tbt2 bit time at 38.4k baud 26.00 us tbt2 bit time at 19.2k baud 52.00 us tbt2 bit time at 9.6k baud 104.00 us tbt2 bit time at 4.8k baud 208.00 us tbt2 bit time at 2.4k baud 416.00 us 0 1 0 1 0 0 1 1 0 1 1 data irrx tbt2 tpw1 notes : 1. irda @ 115k is hpsir compatible. irda @ 2400 will allow compatibility with hp95lx and 48sx. 2. uart1, uart2 0xf1 bit 0 : 1 = receive active low 0 = receive active high (default )
acer laboratories inc. --preliminary, confidential, proprietary-- m512x : mega i/o controller with pnp 07-02-1997 document number: 512xds02.doc page 109 acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, r.o.c. tel: 886-(02) 762-8800 fax: 762-6060 irda transmit timing table 10-15. irda transmit timing symbol parameter min typ max unit tp1 pulse width at 115k baud 1.39 1.60 2.72 s tp1 pulse width at 57.6k baud 1.39 3.22 3.70 s tp1 pulse width at 38.4k baud 1.39 4.80 5.54 s tp1 pulse width at 19.2k baud 1.39 9.70 11.08 s tp1 pulse width at 9.6k baud 1.39 19.50 22.14 s tp1 pulse width at 4.8k baud 1.39 39.00 44.28 s tp1 pulse width at 2.4k baud 1.39 78.00 88.56 s tb2 bit time at 115k baud - 8.68 - s tb2 bit time at 57.6k baud - 17.40 - s tb2 bit time at 38.4k baud - 26.00 - s tb2 bit time at 19.2k baud - 52.00 - s tb2 bit time at 9.6k baud - 104.00 - s tb2 bit time at 4.8k baud - 208.00 - s tb2 bit time at 2.4k baud - 416.00 - s 0 1 0 1 0 0 1 1 0 1 1 data irtx tb2 tp1 notes : 1. irda @ 115k is hpsir compatible. irda @ 2400 will allow compatibility with hp95lx and 48sx. 2. uart1, uart2 0xf1 bit 1 : 1 = transmit active low 0 = transmit active high (default)
--preliminary, confidential, proprietary-- acer laboratories inc. m512x : mega i/o controller with pnp page 110 07-02-1997 document number: 512xds02.doc acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, roc tel: 886-(02) 762-8800 fax: 762-6060 parallel port interrupt timing table 10-16. parallel port interrupt timing symbol parameter min typ max unit t1 pirq delay from ackj, nfault 30 ns t2 pirq active in epp & ecp modes 250 375 ns t1 t1 t2 t1 t2 ackj pirq (spp & ps2) pirq (epp & ecp) nfault (ecp) pirq
acer laboratories inc. --preliminary, confidential, proprietary-- m512x : mega i/o controller with pnp 07-02-1997 document number: 512xds02.doc page 111 acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, r.o.c. tel: 886-(02) 762-8800 fax: 762-6060 epp mode version 1.7 timing table 10-17. epp mode version 1.7 timing symbol parameter min typ max unit t1 iowj active to writej active 45 ns t2 iowj active to writej & dstrbj/astrbj active 45 ns t3 writej active to pd7-0 valid 15 ns t4 waitj active to iochrdyj active 40 ns t5 dstrbj/astrbj inactive to pd7-0 invalid 50 ns sd7-0 iowj iorj writej dstrbj or asrrbj pd7-0 waitj iochrdy t1 t4 t4 t4 t4 t1 t2 t3 t2 t2 t2 t5
--preliminary, confidential, proprietary-- acer laboratories inc. m512x : mega i/o controller with pnp page 112 07-02-1997 document number: 512xds02.doc acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, roc tel: 886-(02) 762-8800 fax: 762-6060 epp mode version 1.9 timing table 10-18. epp mode version 1.9 timing symbol parameter min typ max unit t1 iowj active to writej active 45 ns t2 iowj active to dstrbj/astrbj active 65 ns t3 iowj active to iochrdy active 40 ns t4 waitj inactive to dstrbj/astrbj inactive 105 ns t5 waitj inactive to iochrdyj inactive 40 ns t6 waitj active to writej inactive 85 ns t7 dstrbj/astrbj inactive to pd7-0 invalid 50 ns sd7-0 iowj iorj writej dstrbj or asrrbj pd7-0 waitj iochrdy t1 t3 t5 t3 t5 t2 t4 t4 t6 t4 t7
acer laboratories inc. --preliminary, confidential, proprietary-- m512x : mega i/o controller with pnp 07-02-1997 document number: 512xds02.doc page 113 acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, r.o.c. tel: 886-(02) 762-8800 fax: 762-6060 ecp mode timing table 10-19. ecp mode timing symbol parameter min typ max unit t1 data valid to strobej active 0 ns t2 strobej active to busy active 0 ns t3 busy active to strobej inactive 75 ns t4 strobej inactive to busy inactive 0 35 ms t5 busy inactive to data update 0 1 sec t6 busy inactive to strobej active 0 ns pd7-0 autofdj strobej busy pd7-0 busy ackj autofdj t1 t2 t4 t6 t5 t3 ecp forward timing diagram ecp backward timing diagram t1 t2 t4 t6 t5 t3
--preliminary, confidential, proprietary-- acer laboratories inc. m512x : mega i/o controller with pnp page 114 07-02-1997 document number: 512xds02.doc acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, roc tel: 886-(02) 762-8800 fax: 762-6060 compatible fifo mode timing table 10-20. compatible fifo mode timing symbol parameter min typ max unit t1 data valid to nstrobe active 500 ns t2 nstrobe active pulse width 500 ns t3 data hold from nstrobe inactive 500 ns t4 nstrobe active to busy active 500 ns t5 busy inactive to pdata transing 80 ns pdata nstrobe busy t1 t2 t4 t5 t1 t3 data 1 data 2
acer laboratories inc. --preliminary, confidential, proprietary-- m512x : mega i/o controller with pnp 07-02-1997 document number: 512xds02.doc page 115 acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, r.o.c. tel: 886-(02) 762-8800 fax: 762-6060 parallel interface table 10-21. parallel interface symbol parameter conditions min max unit t pdh port data hold 5 00 ns t pds port data setup 500 ns t pi port interrupt 33 ns t sw strobe width 500 ns interrupt timing >| || || tpds |< >| tpdh |< >| tsw |< busy ackj pd0-pd7 stbj parameter min typ max unit t1 modulated output bit time s t2 off bit time s t3 modulated output ? on ? 0.81 1 1.18 s t4 modulated output ? on ? 0.81 1 1.18 s t5 modulated output ? on ? 0.81 1 1.18 s t6 modulated output ? off ? 0.81 1 1.18 s
--preliminary, confidential, proprietary-- acer laboratories inc. m512x : mega i/o controller with pnp page 116 07-02-1997 document number: 512xds02.doc acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, roc tel: 886-(02) 762-8800 fax: 762-6060 0 1 0 1 0 0 1 1 0 1 1 data irrx t2 t1 mirrx t6 t5 t3 t4 notes : 1. t1, t2 timing referred to irda receive timing @ each baud rate. 2. uart1, uart2 0xf1 bit 0 : 1 = receive active low 0 = receive active high (default ) 3. mirrx are the modulated outputs. ( 500k )
acer laboratories inc. --preliminary, confidential, proprietary-- m512x : mega i/o controller with pnp 07-02-1997 document number: 512xds02.doc page 117 acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, r.o.c. tel: 886-(02) 762-8800 fax: 762-6060 section 11 : packaging information 160 1 40 h d d e h e 5 o 5 o l l 1 e b ? y see detail r c seating plane a detail r a 2 a 1 symbol dimensions in millimeters (nom.) dimensions in inches (nom.) a 3.5 (max) 0.138 (max) a 1 0.20 0.008 a 2 3.20 0.126 b 0.30 0.012 c 0.15 0.006 d 28.0 1.102 e 28.0 1.102 e 0.65 0.026 h d 32.0 1.260 h e 32.0 1.260 l 1 2.01 0.079 l 0.8 0.031 y 0.10 0.004
--preliminary, confidential, proprietary-- acer laboratories inc. m512x : mega i/o controller with pnp page 118 07-02-1997 document number: 512xds02.doc acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, roc tel: 886-(02) 762-8800 fax: 762-6060 section 12 : ordering information ordering information m5123 supports phoenix kbc M5125 supports ami kbc
acer laboratories inc. --preliminary, confidential, proprietary-- m512x : mega i/o controller with pnp 07-02-1997 document number: 512xds02.doc page 119 acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, r.o.c. tel: 886-(02) 762-8800 fax: 762-6060 section 13 : revision history p.28 note : drive table 00 = regular drives and 2.88mb 01 = 3-mode drive p.53 perpendicular mode
--preliminary, confidential, proprietary-- acer laboratories inc. m512x : mega i/o controller with pnp page 120 07-02-1997 document number: 512xds02.doc acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, roc tel: 886-(02) 762-8800 fax: 762-6060 worldwide distributors and sales offices : t aiwan acer laboratories inc. 7f, no. 115 tung hsing street, taipei 110, taiwan, r.o.c. tel: 886 (2) 762 -8800 fax: 886 (2) 762 -6060 acer sertek 11-15f, 135, sec. 2 chien kuo north road, taipei 10479,taiwan, r.o.c. tel: 886 (2) 501-0055 fax: 886 (2) 501- 2521 arrow / ally, inc. 11f, 678, sec. 4, pa teh road, taipei, taiwan, r.o.c. tel: 886 (2) 768 - 6399 fax: 886 (2) 768 - 6390 asec international inc. 4f, 223 chung yang road, nan kang, taipei, taiwan, r.o.c. tel: 886 (2) 786-6677 fax: 886 (2) 786 - 5257 hong kong lestina international ltd. 14/f, park tower 15 austin road, tsimshatsui, hong kong tel: 852-2735 -1736 fax: 852-2730 - 5260 texny glorytact (hk) ltd. unit m, 6/f, kaiser estate phase 3, 11 hok yuen street, hunghom, kowloon, hong kong tel: 852 - 2765 - 0118 fax: 852 - 2765 - 0557 japan ascii corporation 8-1, inarimae, tsukuba-shi ibaraki, 305, japan tel: 81 - 298 - 55 - 4004 fax: 81 - 298 - 55 - 1985 kanematsu electronic components corp. 11f shin-ohsaki kangyo bldg., 6-4, ohsaki 1-chome, shinagawa-ku, tokyo, japan 141 tel: 81 (3) 3779 - 7850 fax: 81 (3) 3779 - 7898 macnica inc. hakusan high-tech park, 1-22-2 hakusan, midori-ku, yokohama city, japan 226 tel: 81 (45) 939 - 6116 fax: 81 (45) 939 - 6117 technova incorporated 9f daiichi-seimei daini bldg., 2-14-27, shin-yokohama, kouhoku-ku, yokohama-shi, kanagawa, 222 tel: 81 (45) 472-7800 fax: 81 (45) 472-7830 korea i&c microsystems co., ltd. 801, 8/f, bethel bldg., 324-1, yangjae-dong, seocho-ku, seoul, korea tel: 82 (2) 577 - 9131 fax: 82 (2) 577 - 9130 singapore electronic resources ltd. 205 kallang bahru, # 04-00, singapore 339341 tel: 65 - 298 - 0888 fax: 65 - 298 - 1111 ali u. s. sales office 1830-b bering drive san jose, ca 95112 usa tel: 1 (408) 467 - 7456 fax: 1 (408) 467 - 7474
acer laboratories inc. --preliminary, confidential, proprietary-- m512x : mega i/o controller with pnp 07-02-1997 document number: 512xds02.doc page 121 acer labs: 7f, 115 tung hsing street, taipei 110, taiwan, r.o.c. tel: 886-(02) 762-8800 fax: 762-6060 this material is recyclable. acer labs products are not licensed for use in medical applications, including, but not limited to, use in life support devices without proper authorization from medical officers. buyers are requested to inform ali sales office when planning to use the products for medical applications. product names used in this publication are for identification purposes only and may be trademarks of their respective companies. acer laboratories inc. makes no warranty for the use of its products and assumes no responsibility for any errors which may appear in this document nor does it make a commitment to update the information contained herein. acer laboratories inc. retains the right to make changes to these specifications at any time, without notice. contact your local sales office to obtain the latest specifications before placing your order. ali is a registered trademark of acer laboratories incorporated and may only be used to identify ali ? s products. ? acer laboratories incorporated 1993

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